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Showing papers by "Jai Narayan Tripathi published in 2020"


Journal ArticleDOI
TL;DR: An efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise is presented.
Abstract: This paper presents an efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise. For this purpose, necessary noise transfer functions are derived and the recently developed EMPSIJ method is advanced to handle cascaded CMOS inverter stages. Results from the proposed method are compared with the results from a conventional EDA simulator, which demonstrate a significant speed-up using the proposed method for a comparable accuracy.

30 citations


Journal ArticleDOI
12 Aug 2020
TL;DR: Two methods are presented, the block approach indefinite admittance matrix (BA-IAM) and the estimation-by-inspection, to analyse the effects of deterministic noise on single-stage, single-ended amplifiers by extending the indefinite admittal matrix.
Abstract: This article presents two methods, the block approach indefinite admittance matrix (BA-IAM) and the estimation-by-inspection, to analyse the effects of deterministic noise on single-stage, single-ended amplifiers by extending the indefinite admittance matrix. The proposed methods are used to develop a generalised two-port network analysis for the commonly used amplifier topologies, in the presence of the supply, ground, bulk, and input noise sources. Various illustrative case studies (common-source, common-gate, and push-pull amplifiers) are considered to validate the analytical method of different CMOS technology nodes (180 nm, 110 nm, and 28 nm) and foundries (Lfoundry, UMC, and TSMC). Both the proposed methods are compared with the relevant existing methods in terms of mean percentage error (MPE), and computational complexity. The mathematically derived expressions using two methods show less than 4% MPE when compared with the schematic simulation results, obtained by the SPICE based simulations. Also, the post-layout simulations (PLS) results for all the examples (designed in CMOS 180 nm Lfoundry technology) show excellent matching with schematic simulations. The proposed methods can be further applicable to antennas, complex circuits, digital circuits, etc.

6 citations


Proceedings ArticleDOI
17 May 2020
TL;DR: In this paper, a generalised indefinite admittance matrix (GIAM) method is proposed to formulate these metrics for active circuits, including the impact of deterministic supply noise on performance parameters.
Abstract: The presence of fluctuations in the power and ground supply rails affect the quality of various performance metrics (gain, phase, impedance, transient response, etc.) of any analog and mixed-signal system. In this paper, a generalised indefinite admittance matrix (GIAM) method is proposed to formulate these metrics for active circuits. The proposed analysis includes the impact of deterministic supply noise on performance parameters. For the purpose of analysis, a common source amplifier, designed in a standard CMOS 180 nm technology, is analysed. The maximum mean percentage error between analytical results and Cadence® Virtuoso® tool simulations for the amplifier is less than 4 % for all the cases.

1 citations


Proceedings ArticleDOI
01 Oct 2020
TL;DR: The estimation by inspection method to analyse the impact of deterministic supply noise on the design specifications of the analog and mixed signal (AMS) systems shows maximum mean percentage error (MPE) of 3% for all the examples.
Abstract: This paper proposes the estimation by inspection method to analyse the impact of deterministic supply noise on the design specifications of the analog and mixed signal (AMS) systems. The method is based on the indefinite admittance matrix (IAM) method. The voltage gain, phase and input-output impedance have been considered as the design specifications. To validate the method, two examples of output stages for analog and digital blocks have been simulated in standard 0.18 $\mu$m technology with 1.8 V of supply and same geometric area. The proposed models using the inspection method and the SPICE based simulations shows maximum mean percentage error (MPE) of 3% for all the examples.

1 citations