Showing papers by "Jai Narayan Tripathi published in 2021"

Device Parameter-Based Analytical Modeling of Power Supply Induced Jitter in CMOS Inverters

Abstract: This article presents an analytical approach to determine jitter for a CMOS inverter in the presence of power supply noise (PSN). The deviation in the transition edge of the output signal from its ideal timing is modeled accurately for each transition. A power series method is used to solve differential equations for different regions of transistors during output transition. The PSN has been expressed in Taylor series expression, aids to derive closed-form equation for time interval error (TIE). The obtained results from the proposed methodology closely match with electronic design automation (EDA) simulator results and verified on 40 nm Taiwan Semiconductor Manufacturing Company (TSMC) and 28 nm United Microelectronics Corporation (UMC) foundries, demonstrating accurate modeling of jitter.

Optimal Design of a Decoupling Network Using Variants of Particle Swarm Optimization Algorithm

Abstract: This paper discusses a discrete optimization problem of optimal design of Power Delivery Networks (PDN) in VLSI systems. In this paper, a practical case study is presented, where, in order to design an efficient PDN, the cumulative impedance of the PDN is optimized below the target impedance. For this purpose, the decoupling capacitors (from commercially available capacitors) are chosen in such a way that the minimum number of the capacitors are used, and also their optimal locations are identified. The different variants of inertia weight strategies incorporated into particle swarm optimization algorithms are used for this purpose. A comparative analysis of the performance of these algorithms is also presented.

Uncertainty Quantification of Memristor Crossbar Array for Vector Matrix Multiplication

Abstract: This work focuses on the study of variability analysis of a memristor-based crossbar. The memristor crossbars are particularly useful in neuromorphic circuits due to their high power efficiency and low latency. This paper presents a variability analysis of the R off to R on ratio due to the change in the parameters of the crossbar cell. A single cell in the crossbar consists of one transistor one memristor (1T1M) based structure. The Zewail-city memristor model is used in the crossbar cell for the analysis. This paper also presents the analysis of the 1T1M structure and 1T1M based crossbar read-write operations. For variability analysis, a stochastic technique named Polynomial Chaos is used and the results are compared with the standard Monte Carlo simulations.

Metaheuristic Optimization of Decoupling Capacitors in a Power Delivery Network

Abstract: In VLSI circuits and systems, it is a common practice to reduce power supply noise in power delivery networks by decoupling capacitors. The optimal selection and placement of decoupling capacitors is crucial for maintaining power integrity efficiently. This paper presents a metaheuristic technique based generic framework for decoupling capacitor optimization in a practical power delivery network. The cumulative impedance of a power delivery network is minimized below the target impedance by optimal selection and placement of decoupling capacitors using state-of-the-art metaheuristic algorithms. A comparative analysis of the performance of these algorithms is presented with the insights of practical implementation.

Analysis of power supply noise in AMS circuits including the effects of interconnects using estimation by inspection method

Abstract: This paper presents the analysis of on-chip analog and mixed signal (AMS) circuits in the presence of supply noise, on- and off-chip interconnect effects. The estimation-by-inspection method is extended to analyze the performance metrics of the AMS circuits. For the purpose of validation, two different examples are considered, designed in UMC 130 nm and Lfoundry 180 nm technology-nodes. The mean percentage error (MPE) between electronic design automation (EDA) simulations and analytical results using the proposed method is less than 10% for various performance metrics of an AMS system. A speed-up factor of 9 has been achieved using the proposed method as compared to the EDA simulations.

An Automated Framework for Variability Analysis using Simulated Annealing

Abstract: In the design process of integrated circuits, design and process variability plays an important role in the performance of the circuits. In this paper, an automated framework for Variability Analysis of CMOS circuits is proposed using simulated annealing algorithm. A practical study of variability analysis of phase noise in a 2.4 GHz CMOS oscillator is illustrated using this framework. The performance for the proposed framework for Variability Analysis application is validated by comparing it with the conventional Monte Carlo simulations. A significant gain in terms of computational time is reported.

Neural-Network Based Modeling of I/O Buffer Predriver under Power/Ground Supply Voltage Variations.

Abstract: This paper presents a neural-network based nonlinear behavioral modelling of I/O buffer that accounts for timing distortion introduced by nonlinear switching behavior of the predriver electrical circuit under power and ground supply voltage (PGSV) variations. Model structure and I/O device characterization along with extraction procedure were described. The last stage of the I/O buffer is modelled as nonlinear current-voltage (I-V) and capacitance voltage (C-V) functions capturing the nonlinear dynamic impedances of the pull-up and pull-down transistors. The mathematical model structure of the predriver was derived from the analysis of the large-signal electrical circuit switching behavior. Accordingly, a generic and surrogate multilayer neural network (NN) structure was considered in this work. Timing series data which reflects the nonlinear switching behavior of the multistage predriver’s circuit PGSV variations, were used to train the NN model. The proposed model was implemented in the time-domain solver and validated against the reference transistor level (TL) model and the state-of-the-art input-output buffer information specification (IBIS) behavioral model under different scenarios. The analysis of jitter was performed using the eye diagrams plotted at different metrics values.

Uncertainty Quantification of a CMOS Oscillator using Stochastic Collocation Techniques

Abstract: In recent years, stochastic techniques have emerged as computationally superior techniques for Uncertainty Quantification (UQ). This paper focuses on the application of different stochastic techniques based on Stochastic Collocation (SC) for UQ. Here, the performance of different SC approaches like interpolation, regression and pseudo-spectral projection is assessed for an illustrative example of a 2.4 GHz CMOS LC oscillator. The application of these approaches for the oscillator circuit is investigated by performing the UQ of its phase noise output. The approaches are further compared with the traditional Monte Carlo simulations. The advantages and disadvantages of each of the methods clearly emerge from our study that helps in choosing the appropriate technique for modeling the uncertainty for any given similar oscillator circuit.

Analytical Modeling of Power Supply Induced Jitter in CMOS Inverters due to Periodic Fluctuations

Abstract: This paper presents an analytical approach to evaluate jitter in the CMOS inverters caused by the periodic fluctuations of the power supply. A closed-form equation of time interval error (TIE) is derived that uses device model parameters to calculate it. In order to derive the output expression for an inverter for various regions of operation which appears during the transition edges, a power series expansion method is used. For the purpose of validation, a 40 nm Ultra Low Power (ULP) commercial technology of TSMC is used with V DD of 1.2 V. The results obtained from the proposed analytical model are verified by comparing them with the simulation results obtained from a standard electronic design automation (EDA) tool, demonstrating an accurate modeling of jitter.

A Study on an IBIS-like Model to Ensure Signal/Power Integrity for I/O Drivers

Abstract: This paper presents a study on non-linear modeling, reported in the state-of-the-art in the last decade for I/O drivers. The study includes the IBIS-like modeling techniques including package parasitics. The IBIS-like model has been analyzed mathematically and validated using 28 nm CMOS technology of TSMC foundry. For validation purposes, the predriver circuit and the I/O buffers have been simulated with 0.9 V of VDD. The IBIS-like nonlinear models have been created using Simulink® and the results have been compared with the Electronic Design Automation (EDA) tools. The Simulink® results show a Normalized Mean Square Error (NMSE) of - 51.91 dB with 1.63 sec of CPU time for the case of pull-up current, -49.42 dB with 474.34 msec of CPU time for the case of pulldown current response. In the case of output voltage response, the NMSE is - 48.33 dB and 2.12 sec of CPU time.

Performance of Crossbar based Long Short Term Memory with Aging Memristors

Abstract: The Long Short Term Memory (LSTM) neural networks find a wide range of applications in time series prediction problems. The long-term accuracy and reliability of LSTM memristor crossbar array are subjected to the memristor device’s endurance and failures. Memristor aging and its impact on such LSTM’s performance is an open problem. This paper analyzes the effects of different types of aging typically exhibited in memristor devices on the crossbar performance. The performance results are analyzed on two datasets, (1) SMS Spam and (2) IMDB movie review. Our analysis indicated that the different aging type shows different performance deterioration levels in the crossbar based LSTM system. Here, the aging analysis for oxide-based memristor implementation are primarily considered when used in CMOS-Memristor hybrid crossbars.