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Author

Jai P. Bansal

Bio: Jai P. Bansal is an academic researcher from BAE Systems. The author has contributed to research in topics: Application-specific integrated circuit & Electronic circuit. The author has an hindex of 5, co-authored 6 publications receiving 210 citations.

Papers
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Patent
Jai P. Bansal1
19 Dec 2002
TL;DR: In this article, a gate array core cell is proposed to reduce the overall wiring lengths, parasitic capacitance, and increase the circuit density and performance of gate array ASIC components, but with the advantage of reducing mask cost and processing time by about 50 percent.
Abstract: A very efficient gate array core cell in which the base core cell consists of a group of 6 PMOS transistors and a group of 6 NMOS transistors. It also includes pre-wiring of 2 of the 6 PMOS transistors, with 2 of the 6 NMOS transistors at polysilicon level or at local interconnect level while leaving the remaining PMOS and NMOS transistors as individual transistors to be interconnected during the functional ASIC metallization process. The core cell also has 2 polysilicon or local interconnect wires embedded in it, which can be used to interconnect transistors for logic function implementation. The core cell defined in this invention is highly flexible and has been analyzed to interconnect all types of logic and memory functions needed for ASIC designs. The layout of the transistors, pre-wiring of the strategic transistors at polysilicon level or at local interconnect level, and embedded polysilicon or local interconnect wires reduce the core cell size significantly. This core cell design reduces the overall wiring lengths, parasitic capacitance, which in turn reduce delays, power dissipation and increase ASIC performance and circuit density. Gate array ASIC components designed using this core cell provide circuit density, performance and power dissipation characteristics comparable to the Standard Cell ASICs but with the advantage of reducing the mask cost and processing time by about 50 percent.

171 citations

Patent
Jai P. Bansal1
05 Aug 2003
TL;DR: In this article, a method for designing a cell-based ASIC device with multiple power supply voltages is described, and the logic blocks are placed on the ASIC so that different voltage groups are separated by at least one cell.
Abstract: A method for designing a cell-based ASIC device with multiple power supply voltages is disclosed. An ASIC chip image is made without applying power or ground buses to metal layer M 1 . All fast or high-power circuits are grouped together into high-power logic blocks and synthesized with high-power circuit macro libraries. All slow or low-power circuits are grouped together into low-power logic blocks and synthesized with low power circuit macro libraries. The associate power and ground buses are applied to metal layer M 1 in each of the logic blocks. The logic blocks are placed on the ASIC so that different voltage groups are separated by at least one cell. The ASIC is then routed and tested before the mask is released.

19 citations

Patent
Jai P. Bansal1
07 Jun 2005
TL;DR: In this paper, a library of logic function macro sets is defined, consisting of one or more micro-circuits with a fixed and complete physical layout similar to a conventional standard cell library macro set.
Abstract: A multi-function core base cell includes a set of functional microcircuits. These microcircuits are used to design a Library of Logic Function Macros. The functional macros consisting of one or more microcircuits have a fixed and complete physical layout similar to a conventional standard cell library macro set. In addition to a core functional macro set, primary input/output buffers and commonly used single and dual port memory blocks are also defined in the library. The library includes all the ASIC synthesis, simulation, and physical design rules.

8 citations

Patent
Jai P. Bansal1
13 Aug 2012
TL;DR: In this paper, a multi-function programmable transceiver is described, which includes a driver circuit and a receiver circuit, which allows an Application Specific Integrated Circuit (ASIC) device to drive and receive data from other ASIC devices.
Abstract: A multi-function programmable transceiver is described. The transceiver includes a driver circuit and a receiver circuit, which allows an Application Specific Integrated Circuit (ASIC) device to drive and receive data from other ASIC devices. Both the driver and receiver circuits share a common input/output (I/O) pin. The driver circuit can be programmed to provide one of the several driver functions, such as CMOS, TTL, PCI, HSTL, SSTL and LVDS. Other functional features of the transceiver that can be programmed are driving strengths or output impedance, output power supply voltage, single ended or differential mode of HSTL/SSTL transceivers, and class 1 or class 2 operations for SSTL/HSTL transceivers. The receiver circuit can also be programmed to provide one of the several receiver functions, such as CMOS, TTL, PCI, HSTL, SSTL and LVDS.

6 citations

Patent
Jai P. Bansal1
15 Dec 2005
TL;DR: In this paper, a pre-driver circuit and enable inputs are decoded in order to provide independent inputs to pull up and pull down transistors in the driver circuit, and a feedback signal generated by the driver output and the driver enable signals controls an inverter circuit within a driver circuit to provide proper biasing conditions at the gate of the pull up transistor.
Abstract: An off chip driver circuit includes a pre-driver circuit and a driver circuit. Driver data and enable inputs are decoded in the pre-driver circuit to provide independent inputs to pull up and pull down transistors in the driver circuit. The enable input keeps the driver circuit in the active or high impedance modes. A feedback signal generated by the driver output and the driver enable signals controls an inverter circuit within the driver circuit to provide proper biasing conditions at the gate of the pull up transistor. This feed back provides fast switching times for the driver circuit and prevents gate oxide of all the transistors from being overstressed by the external high voltage signal.

5 citations


Cited by
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Patent
08 Mar 2007
TL;DR: In this paper, a linear gate electrode track that extends over both a diffusion region and a non-active region of the substrate is defined to minimize a separation distance between ends of adjacent linear gate electrodes segments within the linear-gated electrode track, while ensuring adequate electrical isolation between the adjacent linear gated electrode segments.
Abstract: A semiconductor device includes a substrate and a number of diffusion regions defined within the substrate. The diffusion regions are separated from each other by a non-active region of the substrate. The semiconductor device includes a number of linear gate electrode tracks defined to extend over the substrate in a single common direction. Each linear gate electrode track is defined by one or more linear gate electrode segments. Each linear gate electrode track that extends over both a diffusion region and a non-active region of the substrate is defined to minimize a separation distance between ends of adjacent linear gate electrode segments within the linear gate electrode track, while ensuring adequate electrical isolation between the adjacent linear gate electrode segments.

217 citations

Patent
18 Sep 2009
TL;DR: In this article, a gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction, each of which is fabricated from a respective originating rectangular-shaped layout feature.
Abstract: A semiconductor device is disclosed as having a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. Each of the conductive features within the gate electrode level region has a width less than a wavelength of light used in a photolithography process to fabricate the conductive features. Conductive features within the gate electrode level region form respective PMOS transistor devices and respective NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level region.

182 citations

Patent
11 Jan 2008
TL;DR: In this paper, a method for defining a dynamic array section to be manufactured on a semiconductor chip is described, which includes defining a peripheral boundary of the dynamic array and a manufacturing assurance halo outside the boundary.
Abstract: A method is disclosed for defining a dynamic array section to be manufactured on a semiconductor chip. The method includes defining a peripheral boundary of the dynamic array section. The method also includes defining a manufacturing assurance halo outside the boundary of the dynamic array section. The method further includes controlling chip layout features within the manufacturing assurance halo to ensure that manufacturing of conductive features inside the boundary of the dynamic array section is not adversely affected by chip layout features within the manufacturing assurance halo.

163 citations

Patent
07 Mar 2009
TL;DR: In this article, the vertical connection structures are placed at a number of gridpoints within a vertical connection placement grid so as to provide electrical connectivity between layout features in the lower and higher chip levels.
Abstract: First and second virtual grates are defined as respective sets of parallel virtual lines extending across a layout area in first and second perpendicular directions, respectively. The virtual lines of the first and second virtual grates correspond to placement locations for layout features in lower and higher chip levels, respectively. Each intersection point between virtual lines of the first and second virtual grates is a gridpoint within a vertical connection placement grid. Vertical connection structures are placed at a number of gridpoints within the vertical connection placement grid so as to provide electrical connectivity between layout features in the lower and higher chip levels. The vertical connection structures are placed so as to minimize a number of different spacing sizes between neighboring vertical connection structures across the vertical connection placement grid, while simultaneously minimizing to an extent possible layout area size. The vertical connection structures may be contacts or vias.

152 citations

Patent
06 May 2010
TL;DR: In this paper, a cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to extend parallel to each other.
Abstract: A cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to extend parallel to each other. Each of the linear-shaped diffusion fins is defined to project upward from the substrate along their extent in the first direction. A number of gate level structures are defined to extend in a conformal manner over some of the number of linear-shaped diffusion fins. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins extend in a second direction that is substantially perpendicular to the first direction. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins form gate electrodes of a corresponding transistor. The diffusion fins and gate level structures can be placed in accordance with a diffusion fin virtual grate and a gate level virtual grate, respectively.

139 citations