Recent years have seen a rapid growth of interest by the scientific and engineering communities in the thermal properties of materials. Heat removal has become a crucial issue for continuing progress in the electronic industry, and thermal conduction in low-dimensional structures has revealed truly intriguing features. Carbon allotropes and their derivatives occupy a unique place in terms of their ability to conduct heat. The room-temperature thermal conductivity of carbon materials span an extraordinary large range--of over five orders of magnitude--from the lowest in amorphous carbons to the highest in graphene and carbon nanotubes. Here, I review the thermal properties of carbon materials focusing on recent results for graphene, carbon nanotubes and nanostructured carbon materials with different degrees of disorder. Special attention is given to the unusual size dependence of heat conduction in two-dimensional crystals and, specifically, in graphene. I also describe the prospects of applications of graphene and carbon materials for thermal management of electronics.

Thermal properties of graphene and nanostructured carbon materials

Recent years witnessed a rapid growth of interest of scientific and engineering communities to thermal properties of materials. Carbon allotropes and derivatives occupy a unique place in terms of their ability to conduct heat. The room-temperature thermal conductivity of carbon materials span an extraordinary large range – of over five orders of magnitude – from the lowest in amorphous carbons to the highest in graphene and carbon nanotubes. I review thermal and thermoelectric properties of carbon materials focusing on recent results for graphene, carbon nanotubes and nanostructured carbon materials with different degrees of disorder. A special attention is given to the unusual size dependence of heat conduction in two-dimensional crystals and, specifically, in graphene. I also describe prospects of applications of graphene and carbon materials for thermal management of electronics.

Thermal Properties of Graphene, Carbon Nanotubes and Nanostructured Carbon Materials

Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

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Fundamentals of Modern VLSI Devices

We present the science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems, targeting an evolution in technology, that might lead to impacts and benefits reaching into most areas of society. This roadmap was developed within the framework of the European Graphene Flagship and outlines the main targets and research areas as best understood at the start of this ambitious project. We provide an overview of the key aspects of graphene and related materials (GRMs), ranging from fundamental research challenges to a variety of applications in a large number of sectors, highlighting the steps necessary to take GRMs from a state of raw potential to a point where they might revolutionize multiple industries. We also define an extensive list of acronyms in an effort to standardize the nomenclature in this emerging field.

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Science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems

High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

A model describing the maximum clock frequency (FMAX) distribution of a microprocessor is derived and compared with wafer sort data for a recent 0.25-/spl mu/m microprocessor. The model agrees closely with measured data in mean, variance, and shape. Results demonstrate that within-die fluctuations primarily impact the FMAX mean and die-to-die fluctuations determine the majority of the FMAX variance. Employing rigorously derived device and circuit models, the impact of die-to-die and within-die parameter fluctuations on future FMAX distributions is forecast for the 180, 130, 100, 70, and 50-nm technology generations. Model predictions reveal that systematic within-die fluctuations impose the largest performance degradation resulting from parameter fluctuations. Assuming a 3/spl sigma/ channel length deviation of 20%, projections for the 50-nm technology generation indicate that essentially a generation of performance gain can be lost due to systematic within-die fluctuations. Key insights from this work elucidate the recommendations that manufacturing process controls be targeted specifically toward sources of systematic within-die fluctuations, and the development of new circuit design methodologies be aimed at suppressing the effect of within-die parameter fluctuations.

http://eda.ee.ucla.edu/EE201A-04Spring/GIT-PV.pdf

Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration

Reductions in CMOS SRAM cell static noise margin (SNM) due to intrinsic threshold voltage fluctuations in uniformly doped minimum-geometry cell MOSFETs are investigated for the first time using compact physical and stochastic models. Six sigma deviations in SNM due to intrinsic fluctuations alone are projected to exceed the nominal SMM for sub-100-nm CMOS technology generations. These large deviations pose severe barriers to scaling of supply voltage, channel length, and transistor count for conventional 6T SRAM-dominated CMOS ASICs and microprocessors.

The impact of intrinsic device fluctuations on CMOS SRAM cell stability

Graphene nanoribbons (GNRs) with widths down to 16 nm have been characterized for their current-carrying capacity. It is found that GNRs exhibit an impressive breakdown current density, on the order of 10^8 A/cm2. The breakdown current density is found to have a reciprocal relationship to GNR resistivity and the data fit points to Joule heating as the likely mechanism of breakdown. The superior current-carrying capacity of GNRs will be valuable for their application in on-chip electrical interconnects. The thermal conductivity of sub-20 nm graphene ribbons is found to be more than 1000 W/m-K.

Breakdown Current Density of Graphene Nano Ribbons

Graphene nanoribbons (GNRs) with widths down to 16 nm have been characterized for their current-carrying capacity. It is found that GNRs exhibit an impressive breakdown current density, on the order of 108 A/cm2. The breakdown current density is found to have a reciprocal relationship to GNR resistivity and the data fit points to Joule heating as the likely mechanism of breakdown. The superior current-carrying capacity of GNRs will be valuable for their application in on-chip electrical interconnects. The thermal conductivity of sub-20 nm graphene ribbons is found to be more than 1000 W/m K.

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Breakdown current density of graphene nanoribbons

Throughout the past four decades, silicon semiconductor technology has advanced at exponential rates in both performance and productivity. Concerns have been raised, however, that the limits of silicon technology may soon be reached. Analysis of fundamental, material, device, circuit, and system limits reveals that silicon technology has an enormous remaining potential to achieve terascale integration (TSI) of more than 1 trillion transistors per chip. Such massive-scale integration is feasible assuming the development and economical mass production of double-gate metal-oxide-semiconductor field effect transistors with gate oxide thickness of about 1 nanometer, silicon channel thickness of about 3 nanometers, and channel length of about 10 nanometers. The development of interconnecting wires for these transistors presents a major challenge to the achievement of nanoelectronics for TSI.

https://science.sciencemag.org/content/sci/293/5537/2044.full.pdf

James D. Meindl

Papers

Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration

The impact of intrinsic device fluctuations on CMOS SRAM cell stability

Breakdown Current Density of Graphene Nano Ribbons

Breakdown current density of graphene nanoribbons

Limits on Silicon Nanoelectronics for Terascale Integration