http://theory.cm.utexas.edu/henkelman/pubs/henkelman06_354.pdf

A fast and robust algorithm for Bader decomposition of charge density

Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

/pdf/fundamentals-of-modern-vlsi-devices-471xd7l9pf.pdf

Fundamentals of Modern VLSI Devices

Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

Tunnel field-effect transistors as energy-efficient electronic switches

Point defects and impurities strongly affect the physical properties of materials and have a decisive impact on their performance in applications. First-principles calculations have emerged as a powerful approach that complements experiments and can serve as a predictive tool in the identification and characterization of defects. The theoretical modeling of point defects in crystalline materials by means of electronic-structure calculations, with an emphasis on approaches based on density functional theory (DFT), is reviewed. A general thermodynamic formalism is laid down to investigate the physical properties of point defects independent of the materials class (semiconductors, insulators, and metals), indicating how the relevant thermodynamic quantities, such as formation energy, entropy, and excess volume, can be obtained from electronic structure calculations. Practical aspects such as the supercell approach and efficient strategies to extrapolate to the isolated-defect or dilute limit are discussed. Recent advances in tractable approximations to the exchange-correlation functional ($\mathrm{DFT}+U$, hybrid functionals) and approaches beyond DFT are highlighted. These advances have largely removed the long-standing uncertainty of defect formation energies in semiconductors and insulators due to the failure of standard DFT to reproduce band gaps. Two case studies illustrate how such calculations provide new insight into the physics and role of point defects in real materials.

First-principles calculations for point defects in solids

Materials research plays a vital role in transforming breakthrough scientific ideas into next-generation technology. Similar to the way silicon revolutionized the microelectronics industry, the proper materials can greatly impact the field of plasmonics and metamaterials. Currently, research in plasmonics and metamaterials lacks good material building blocks in order to realize useful devices. Such devices suffer from many drawbacks arising from the undesirable properties of their material building blocks, especially metals. There are many materials, other than conventional metallic components such as gold and silver, that exhibit metallic properties and provide advantages in device performance, design flexibility, fabrication, integration, and tunability. This review explores different material classes for plasmonic and metamaterial applications, such as conventional semiconductors, transparent conducting oxides, perovskite oxides, metal nitrides, silicides, germanides, and 2D materials such as graphene. This review provides a summary of the recent developments in the search for better plasmonic materials and an outlook of further research directions.

/pdf/alternative-plasmonic-materials-beyond-gold-and-silver-1p8fd7ol50.pdf

Alternative Plasmonic Materials: Beyond Gold and Silver

Diffusion in silicon of elements from columns III and V of the Periodic Table is reviewed in theory and experiment. The emphasis is on the interactions of these substitutional dopants with point defects (vacancies and interstitials) as part of their diffusion mechanisms. The goal of this paper is to unify available experimental observations within the framework of a set of physical models that can be utilized in computer simulations to predict diffusion processes in silicon. The authors assess the present state of experimental data for basic parameters such as point-defect diffusivities and equilibrium concentrations and address a number of questions regarding the mechanisms of dopant diffusion. They offer illustrative examples of ways that diffusion may be modeled in one and two dimensions by solving continuity equations for point defects and dopants. Outstanding questions and inadequacies in existing formulations are identified by comparing computer simulations with experimental results. A summary of the progress made in this field in recent years and of directions future research may take is presented.

Point defects and dopant diffusion in silicon

Accurate modeling of MOS devices requires quantitative knowledge of carrier mobilities in surface inversion and accumulation layers. Optimization of device structures and accurate circuit simulation, particulary as technologies push toward fundamental limits, necessitate an understanding of how impurity doping levels, oxide charge densities, process techniques, and applied electric fields affect carrier surface mobilities. It is the purpose of this paper to present an extensive set experimental results on the behavior of electron surface mobility in thermally oxidized silicon structures. Empirical equations are developed which allow the calculation of electron mobility under a wide variety of substrate, process, and electrical conditions. The experimental results are interpreted in terms of the dominant physical mechanisms responsible for mobility degradation at the Si/SiO 2 interface. From the observed effects of process parameters on mobility roll-off under high vertical fields, conclusions are drawn about optimum process conditions for maximizing mobility. The implications of this work for performance limits of several types of MOS devices are described.

Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces

We present a scaling theory for fully-depleted, cylindrical MOSFET's. This theory was derived from the cylindrical form of Poisson's equation by assuming a parabolic potential in the radial direction. Numerical device simulation data for subthreshold slope and DIBL were compared to the model to validate the formula. By employing the scaling theory a comparison with double-gate (DG) MOSFET's was carried out illustrating an improvement of up to 40% in the minimum effective channel length for the cylindrical device.

Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's

(NOTE: Chapters 3-11 include an Introduction, Historical Development and Basic Concepts, Manufacturing Methods and Equipment, Measurement Methods, Models and Simulation, Limits and Future Trends in Technologies and Models, Summary of Key Ideas, References, and Problems.) 1. Introduction and Historical Perspective. Introduction. Integrated Circuits and the Planar Process-Key Inventions That Made It All Possible. Semiconductors. Semiconductor Devices. Semiconductor Circuit Families. Modern Scientific Discovery-Experiments, Theory and Computer Simulation. The Plan for This Book. 2. Modern CMOS Technology. CMOS Process Flow. 3. Crystal Growth, Wafer Fabrication and Basic Properties of Silicon Wafers. 4. Semiconductor Manufacturing- Clean Rooms, Wafer Cleaning and Gettering. 5. Lithography. 6. Thermal Oxidation and the Si/SiO2 Interface. 7. Dopant Diffusion. 8. Ion Implantation. 9. Thin Film Deposition. 10. Etching. 11. Backend Technology.

Silicon VLSI Technology: Fundamentals, Practice and Modeling

One of the "fundamental" problems in the continued scaling of MOSFETs is the 60 mV/decade room temperature limit in subthreshold slope. In this paper, we report initial studies on a new kind of transistor, the I-MOS. The I-MOS uses modulation of the breakdown voltage of a gated p-i-n structure in order to switch from the OFF to the ON state and vice versa. Since impact-ionization is an abrupt function of the electric field (or the carrier energy), simulations show that the device has a subthreshold slope much lower than kT/q. Simulations also show that it is indeed possible to make complementary circuits with switching speeds comparable to or exceeding CMOS. Experimental results on a silicon based prototype verify the basic concept and show very steep subthreshold slopes with high speed turn-on and turn-off. Lower bandgap materials are also being investigated to reduce the value of the breakdown voltage and permit lower voltage operation.

James D. Plummer

Papers

Point defects and dopant diffusion in silicon

Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces

Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's

Silicon VLSI Technology: Fundamentals, Practice and Modeling

I-MOS: a novel semiconductor device with a subthreshold slope lower than kT/q