James F. Buckwalter

Bio: James F. Buckwalter is an academic researcher from University of California, Santa Barbara. The author has contributed to research in topics: Amplifier & CMOS. The author has an hindex of 29, co-authored 233 publications receiving 3341 citations. Previous affiliations of James F. Buckwalter include IBM & California Institute of Technology.

Analysis and Design of Stacked-FET Millimeter-Wave Power Amplifiers

Abstract: Stacked field-effect transistor (FET) CMOS millimeter-wave power amplfiers (PAs) are studied with a focus on design of appropriate complex impedances between the transistors. The stacking of multiple FETs allows increasing the supply voltage, which, in turn, allows higher output power and a broader bandwidth output matching network. Different matching techniques for the intermediate nodes are analyzed and used in two-, three-, and four-stack single-stage $Q$ -band CMOS PAs. A four-stack amplifier design achieves a saturated output power greater than 21 dBm while achieving a maximum power-added efficiency (PAE) greater than 20% from 38 to 47 GHz. The effectiveness of an inductive tuning technique is demonstrated in measurement, improving the PAE from 26% to 32% in a two-stack PA design. The input and output matching networks are designed using on-chip shielded coplanar waveguide transmission lines, as well as metal finger capacitors. The amplifiers were implemented in a 45-nm CMOS silicon-on-insulator process. Each of the amplifiers occupies an area of 600 $\mu$ m $\,\times\,$ 500 $\mu$ m including pads.

A Monolithic 25-Gb/s Transceiver With Photonic Ring Modulators and Ge Detectors in a 130-nm CMOS SOI Process

Abstract: A fully-integrated, silicon photonic transceiver is demonstrated in a silicon-on-insulator process using photonic microring resonator modulators for low power consumption. The trade-offs between bandwidth and extinction ratio are discussed and motivate the use of transmit pre-emphasis for ring modulators to increase the interconnect data rate. The transmitter and receiver is demonstrated to data rates of 25 Gb/s with a BER of 10 ^-12. The total power consumption of the transceiver is 256 mW and demonstrates a link efficiency of 10.2 pJ/bit excluding laser power. At 25 Gb/s, the driver operates at 7.2 pJ/bit.

Bandwidth Enhancement With Low Group-Delay Variation for a 40-Gb/s Transimpedance Amplifier

Abstract: A 40-Gb/s transimpedance amplifier (TIA) is proposed using multistage inductive-series peaking for low group-delay variation. A transimpedance limit for multistage TIAs is derived, and a bandwidth-enhancement technique using inductive-series π -networks is analyzed. A design method for low group delay constrained to 3-dB bandwidth enhancement is suggested. The TIA is implemented in a 0.13-μm CMOS process and achieves a 3-dB bandwidth of 29 GHz. The transimpedance gain is 50 dB·Ω , and the transimpedance group-delay variation is less than 16 ps over the 3-dB bandwidth. The chip occupies an area of 0.4 mm2, including the pads, and consumes 45.7 mW from a 1.5-V supply. The measured TIA demonstrates a transimpedance figure of merit of 200.7 Ω/pJ.

Cancellation of crosstalk-induced jitter

Abstract: A novel jitter equalization circuit is presented that addresses crosstalk-induced jitter in high-speed serial links. A simple model of electromagnetic coupling demonstrates the generation of crosstalk-induced jitter. The analysis highlights unique aspects of crosstalk-induced jitter that differ from far-end crosstalk. The model is used to predict the crosstalk-induced jitter in 2-PAM and 4-PAM, which is compared to measurement. Furthermore, the model suggests an equalizer that compensates for the data-induced electromagnetic coupling between adjacent links and is suitable for pre- or post-emphasis schemes. The circuits are implemented using 130-nm MOSFETs and operate at 5-10 Gb/s. The results demonstrate reduced deterministic jitter and lower bit-error rate (BER). At 10 Gb/s, the crosstalk-induced jitter equalizer opens the eye at 10/sup -12/ BER from 17 to 45 ps and lowers the rms jitter from 8.7 to 6.3 ps.

A Case for Digital Beamforming at mmWave

Abstract: Due to the heavy reliance of millimeter-wave (mmWave) wireless systems on directional links, beamforming (BF) with high-dimensional arrays is essential for cellular systems in these frequencies. Thus, performing the array processing in a power-efficient manner is a fundamental challenge. Analog and hybrid BF require few analog-to-digital and digital-to-analog converters (ADCs and DACs), but can only communicate in a small number of directions at a time, limiting directional search, spatial multiplexing, and control signaling. Digital BF enables flexible spatial processing but must be operated at a low quantization resolution to stay within reasonable power levels. This decrease in quantizer resolution distorts the received as well as the transmitted signal. To assess the effect of coarse quantization at the receiver, this paper presents a system level analytic framework based on a simple additive quantization noise model (AQNM). The analysis verified through extensive simulations reveals that at moderate resolutions (3–4 bits per ADC), there is negligible loss in downlink cellular capacity from quantization. In essence, the low resolution ADCs limit the high SNR, where cellular systems typically do not operate. For the transmitter, it is shown that DACs with 4 or more bits of resolution can support high order modulations, and do not violate the adjacent carrier leakage limit set by 3rd Generation Partnership Project (3GPP) New Radio (NR) standards for cellular operations. In fact, our findings suggest that low resolution digital BF architectures can be a power-efficient alternative to analog or hybrid BF for both transmitters and receivers at millimeter-wave.

Single-chip microprocessor that communicates directly using light

Abstract: An electronic–photonic microprocessor chip manufactured using a conventional microelectronics foundry process is demonstrated; the chip contains 70 million transistors and 850 photonic components and directly uses light to communicate to other chips. The rapid transfer of data between chips in computer systems and data centres has become one of the bottlenecks in modern information processing. One way of increasing speeds is to use optical connections rather than electrical wires and the past decade has seen significant efforts to develop silicon-based nanophotonic approaches to integrate such links within silicon chips, but incompatibility between the manufacturing processes used in electronics and photonics has proved a hindrance. Now Chen Sun et al. describe a 'system on a chip' microprocessor that successfully integrates electronics and photonics yet is produced using standard microelectronic chip fabrication techniques. The resulting microprocessor combines 70 million transistors and 850 photonic components and can communicate optically with the outside world. This result promises a way forward for new fast, low-power computing systems architectures. Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems—from mobile phones to large-scale data centres. These limitations can be overcome1,2,3 by using optical communications based on chip-scale electronic–photonic systems4,5,6,7 enabled by silicon-based nanophotonic devices8. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic–photonic chips9,10,11 are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic–photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a ‘zero-change’ approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics12, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors13,14,15,16. This demonstration could represent the beginning of an era of chip-scale electronic–photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

Design Of Analog Cmos Integrated Circuits

Abstract: Thank you very much for downloading design of analog cmos integrated circuits. Maybe you have knowledge that, people have look hundreds times for their favorite novels like this design of analog cmos integrated circuits, but end up in malicious downloads. Rather than reading a good book with a cup of coffee in the afternoon, instead they cope with some malicious virus inside their laptop. design of analog cmos integrated circuits is available in our book collection an online access to it is set as public so you can download it instantly. Our digital library saves in multiple countries, allowing you to get the most less latency time to download any of our books like this one. Merely said, the design of analog cmos integrated circuits is universally compatible with any devices to read.

State of the Art in 60-GHz Integrated Circuits and Systems for Wireless Communications

Abstract: This tutorial presents an overview of the technological advances in millimeter-wave (mm-wave) circuit components, antennas, and propagation that will soon allow 60-GHz transceivers to provide multigigabit per second (multi-Gb/s) wireless communication data transfers in the consumer marketplace. Our goal is to help engineers understand the convergence of communications, circuits, and antennas, as the emerging world of subterahertz and terahertz wireless communications will require understanding at the intersections of these areas. This paper covers trends and recent accomplishments in a wide range of circuits and systems topics that must be understood to create massively broadband wireless communication systems of the future. In this paper, we present some evolving applications of massively broadband wireless communications, and use tables and graphs to show research progress from the literature on various radio system components, including on-chip and in-package antennas, radio-frequency (RF) power amplifiers (PAs), low-noise amplifiers (LNAs), voltage-controlled oscillators (VCOs), mixers, and analog-to-digital converters (ADCs). We focus primarily on silicon-based technologies, as these provide the best means of implementing very low-cost, highly integrated 60-GHz mm-wave circuits. In addition, the paper illuminates characterization techniques that are required to competently design and fabricate mm-wave devices in silicon, and illustrates effects of the 60-GHz RF propagation channel for both in-building and outdoor use. The paper concludes with an overview of the standardization and commercialization efforts for 60-GHz multi-Gb/s devices, and presents a novel way to compare the data rate versus power efficiency for future broadband devices.

Millimeter-Wave Communications: Physical Channel Models, Design Considerations, Antenna Constructions, and Link-Budget

Abstract: The millimeter wave (mmWave) frequency band spanning from 30 to 300 GHz constitutes a substantial portion of the unused frequency spectrum, which is an important resource for future wireless communication systems in order to fulfill the escalating capacity demand. Given the improvements in integrated components and enhanced power efficiency at high frequencies, wireless systems can operate in the mmWave frequency band. In this paper, we present a survey of the mmWave propagation characteristics, channel modeling, and design guidelines, such as system and antenna design considerations for mmWave, including the link budget of the network, which are essential for mmWave communication systems. We commence by introducing the main channel propagation characteristics of mmWaves followed by channel modeling and design guidelines. Then, we report on the main measurement and modeling campaigns conducted in order to understand the mmWave band’s properties and present the associated channel models. We survey the different channel models focusing on the channel models available for the 28, 38, 60, and 73 GHz frequency bands. Finally, we present the mmWave channel model and its challenges in the context of mmWave communication systems design.