Power-on-reset logic is included within an integrated circuit. The power-on-reset logic includes a power-on-reset cell. The power-on-reset cell causes a reset signal to be issued upon a power signal being connected to the integrated circuit. The power-on-reset cell includes a power down input connected to a power-down line. When a power-down signal is placed on the power-down line, the power-on-reset cell is inactivated so that the power-on-reset cell does not cause the reset signal to be issued upon the power signal being connected to the integrated circuit. The power-on-reset logic also includes a logic block connected to the power-down line and to a system clock. The logic block issues a reset when the power-down signal is placed on the power-down line and the system clock is active. For example, the logic block is a delay (D) flip-flop having a D input connected to the power down line and a clock input connected to the system clock.

Power-on-reset logic with secure power down capability

An internal sampling capacitor of an analog-to-digital converter (ADC) in a digital device is charged to a reference voltage, then some of the voltage charge on the internal.sampling capacitor is transferred to an external unknown capacitor through a low resistance switch internal to the digital device. After the charge transfer has stabilized, the voltage charge remaining on the internal sampling capacitor is measured. The difference between the known reference voltage and the voltage remaining on the internal sampling capacitor is used to determine the capacitance value of the external capacitor. Alternatively, the external capacitor may be charged to a reference voltage then the external capacitor is coupled to the internal sampling capacitor, e.g., having no charge or a known charge on it, and the resulting voltage charge on the internal sampling capacitor is measured and used for determining the capacitance value of the external capacitor.

Capacitive touch sensing using an internal capacitor of an analog-to-digital converter (adc) and a voltage reference

Some embodiments described herein include a system that collects and learns reference side-channel normal activity, process it to reveal key features, compares subsequent collected data and processed data for anomalous behavior, and reports such behavior to a management center where this information is displayed and predefine actions can be executed when anomalous behavior is observed. In some instances, a physical side channel (e.g. and indirect measure of program execution such as power consumption or electromagnetic emissions and other physical signals) can be used to assess the execution status in a processor or digital circuit using an external monitor and detect, with extreme accuracy, when an unauthorized execution has managed to disrupt the normal operation of a target system (e.g., a computer system, etc.).

Systems, methods, and apparatuses for intrusion detection and analytics using power characteristics such as side-channel information collection

Circuitry for controlling the oscillation frequency of an oscillator by using a digitally tunable on-chip capacitor bank The capacitor bank includes a plurality of on-chip capacitors, each of which is independently selectable by a control signal for providing a selectable amount of capacitance to the oscillator to control the oscillator's oscillation frequency

Oscillator with tunable capacitor

A capacitance measurement circuit and method are provided. A storage capacitor is pre-charged. Charge transfer is performed between an under-test capacitor and the storage capacitor. The storage capacitor is discharged and charged according to a relationship between a voltage of the storage capacitor and a reference voltage. The capacitance of the under-test capacitor is measured according to the voltage on the storage capacitor.

Capacitance measurement circuit and method

A method and apparatus for performing power on reset initialization in a data processing system (40). In one form, the present invention uses a circuit (71) to ensure that a node (65) always power up to the correct logic level. This node (65) can then be used to initialize a latch (83) so that the latch (83) always drives a predetermined logic level at its data output when the latch (83) powers up. The data output of latch (83) is a Power On Reset signal which is asserted during power on reset initialization and which is negated when power on reset initialization is completed.

Method and apparatus for performing power on reset initialization in a data processing system

An on-chip protection network is introduced providing high immunity to component and system level stress. It uses active MOSFET rail clamps with novel RC triggering and clamp layout schemes.

http://ieeexplore.ieee.org/iel7/6619544/6635896/06635927.pdf

An active MOSFET rail clamp network for component and system level protection

A method and apparatus for limiting access to an integrated circuit (IC) upon detection of abnormal conditions is provided. At least one of abnormal voltage detection, abnormal temperature detection, and abnormal clock detection are provided with low power consumption. Both abnormally low and abnormally high parameter values (e.g. abnormally low or high voltage, temperature, or clock frequency) may be detected. Abnormal clock detection may also detect a stopped clock signal, including a clock signal stopped at a low logic level or at a high logic level. Furthermore, abnormal clock detection may detect an abnormal duty cycle of a clock signal. A sampled bandgap reference may be used to provide accurate voltage and current references while consuming a minimal amount of power. Upon detection of an abnormal parameter value, one or more tamper indications may be provided to initiate tampering countermeasures, such as limiting access to the IC.

Method and apparatus for limiting access to an integrated circuit (IC)

A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.

Method and apparatus for self-test of successive approximation register (SAR) A/D converter

A data converter for converting analog signals to digital signals, or for converting digital signals to analog signals is provided. In one embodiment, a production self-test is provided. In one embodiment, a high-speed lower-resolution method or mode for a data converter is provided. In one embodiment, a differential data converter with a more stable comparator common mode voltage is provided. In one embodiment, the input range of a digitally calibrated data converter is provided and maintained so that there is no loss in input range due to the calibration. In one embodiment, digital post-processing of an uncalibrated result using a previously stored calibration value is provided.

James R. Feddeler

Papers

Method and apparatus for performing power on reset initialization in a data processing system

An active MOSFET rail clamp network for component and system level protection

Method and apparatus for limiting access to an integrated circuit (IC)

Method and apparatus for self-test of successive approximation register (SAR) A/D converter

Method and apparatus for testing data converter