James Z. Ma

Bio: James Z. Ma is an academic researcher from Cadence Design Systems. The author has contributed to research in topics: Electronic design automation. The author has an hindex of 1, co-authored 1 publications receiving 55 citations.

Design tools for reliability analysis

Abstract: Recent progress in EDA tools allows IC designs to be accurately verified with consequent improvements in yield and performance through reduced guard bands. This paper will present a tools perspective, including the primary effects such as HCI, NBTI and EM for which EDA tools are available, types of tools (dynamic simulation vs. static rule checking) and necessary reliability infrastructure and flows that have been working in practice. Finally, developing areas and future opportunities will be addressed.

Sensing nanosecond-scale voltage attacks and natural transients in FPGAs

Abstract: Voltage noise not only detracts from reliability and performance, but has been used to attack system security. Most systems are completely unaware of fluctuations occurring on nanosecond time scales. This paper quantifies the threat to FPGA-based systems and presents a solution approach. Novel measurements of transients on 28nm FPGAs show that extreme activity in the fabric can cause enormous undershoot and overshoot, more than 10× larger than what is allowed by the specification. An existing voltage sensor is evaluated and shown to be insufficient. Lastly, a sensor design using reconfigurable logic is presented; its time-to-digital converter enables sample rates 500× faster than the 28nm Xilinx ADC. This enables quick characterization of transients that would normally go undetected, thereby providing potentially useful data for system optimization and helping to defend against supply voltage attacks.

Towards interdependencies of aging mechanisms

Abstract: With technology in deep nano scale, the susceptibility of transistors to various aging mechanisms such as Negative/ Positive Bias Temperature Instability (NBTI/PBTI) and Hot Carrier Induced Degradation (HCID) etc. is increasing. As a matter of fact, different aging mechanisms simultaneously occur in the gate dielectric of a transistor. In addition, scaling in conjunction with high-K materials has made aging mechanisms, that have often been assumed to be negligible (e.g., PBTI in NMOS and HCID in PMOS), become noticeable. Therefore, in this paper we investigate the key challenge of providing designers with an abstracted, yet accurate reliability estimation that combines, from the physical to system level, the effects of multiple simultaneous aging mechanisms and their interdependencies. We show that the overall aging can be modeled as a superposition of the interdependent aging effects. Our presented model deviates by around 6% from recent industrial physical measurements. We conclude from our experiments that an isolated treatment of individual aging mechanisms is insufficient to devise effective mitigation strategies in current and upcoming technology nodes. We also demonstrate that estimating reliability due to an individual dominant aging mechanism together with solely considering a single kind of failures, as currently is a main focus of state-of-the-art (e.g., [28], [22]), can result in 75% underestimation on average.

Compact Modeling of Statistical BTI Under Trapping/Detrapping

Abstract: The aging process due to negative bias temperature instability (NBTI) is a key limiting factor of circuit lifetimes in CMOS design. Recent NBTI data exhibits an excessive amount of randomness and fast recovery, which are difficult to be handled by conventional power-law model (tn). Such discrepancies further pose the challenge on long-term reliability prediction under statistical variations and dynamic voltage scaling (DVS) in real circuit operation. To overcome these barriers, this paper: 1) practically explains the aging statistics due to randomness in number of traps with the log(t) model, accurately predicting the mean and variance shift; 2) proposes cycle-to-cycle model (from the first principles of trapping) to handle aging under multiple supply voltages, predicting the nonmonotonic behavior under DVS; 3) presents a long-term model to estimate a tight upper bound of dynamic aging over multiple cycles; and 4) comprehensively validates the new set of aging models with 65-nm statistical silicon data. Compared with previous models, the new set of aging models capture the aging variability and the essential role of the recovery phase under DVS, reducing unnecessary guard banding during the design stage.

Aging analysis at gate and macro cell level

Abstract: Aging, which can be regarded as a time-dependent variability, has until recently not received much attention in the field of electronic design automation. This is changing because increasing reliability costs threaten the continued scaling of ICs. We investigate the impact of aging effects on single combinatorial gates and present methods that help to reduce the reliability costs by accurately analyzing the performance degradation of aged circuits at gate and macro cell level.