Jamil A. Wakil

Bio: Jamil A. Wakil is an academic researcher from IBM. The author has contributed to research in topics: Flip chip & Thermal resistance. The author has an hindex of 13, co-authored 34 publications receiving 1001 citations.

Hotspot-Limited Microprocessors: Direct Temperature and Power Distribution Measurements

Abstract: An experimental technique is presented, which allows for spatially-resolved imaging of microprocessor power (SIMP). In a first step this method utilizes infrared (IR) thermal imaging, while the processor is effectively cooled using an IR-transparent heat sink. In the second step the underlying power distribution is derived by determining the temperature fields for each individual power source on the chip. The measured chip temperature distribution is represented as a superposition of these temperature fields. The SIMP data reveals significant temporal and spatial variations of the microprocessor power/temperature distribution, which can be attributed to the circuit layout as well as to the varying utilization levels across the processor while running full workloads. In this paper we have applied the SIMP method to the dual core PowerPCtrade970MP microprocessor to measure detailed temperature and power distributions under full operating conditions. In the first part of the paper the impact of power and temperature limitations of high performance CMOS chips is discussed in detail, where we distinguish between hotspot-limited (or temperature-limited) and power-limited chips. The discussion shows the importance of temperature and power distributions for chip floor planning, layout, design and architecture. Second, we present the experimental details of the SIMP method, which is applied to the dual core PowerPC970MP to directly measure the temperature and power fields as a function of workload and frequency. A pronounced movement of the hotspot location is observed. Finally, the hotspot of a competitive microprocessor is compared by measuring temperature efficiencies (temperature increase/performance) for the same workloads and cooling conditions

A Practical Implementation of Silicon Microchannel Coolers for High Power Chips

Abstract: This paper describes a practical implementation of a single-phase Si microchannel cooler designed for cooling very high power chips such as microprocessors. Through the use of multiple heat exchanger zones and optimized cooler fin designs, a unit thermal resistance 10.5 C-mm2 /W from the cooler surface to the inlet water was demonstrated with a fluid pressure drop of <35kPa. Further, cooling of a thermal test chip with a microchannel cooler bonded to it packaged in a single chip module was also demonstrated for a chip power density greater than 300W/cm2. Coolers of this design should be able to cool chips with average power densities of 400W/cm2 or more

A practical implementation of silicon microchannel coolers for high power chips

Abstract: The paper describes a practical implementation of a single-phase Si microchannel cooler designed for cooling very high power chips such as microprocessors. Through the use of multiple heat exchanger zones and optimized cooler fin designs, a unit thermal resistance of 10.5 C-mm/sup 2//W from the cooler surface to the inlet water was demonstrated with a fluid pressure drop of less than 35 kPa. Further, cooling of a thermal test chip with a microchannel cooler bonded to it packaged in a single chip module was also demonstrated for a chip power density greater than 300 W/cm/sup 2/. Coolers of this design should be able to cool chips with average power densities of 400 W/cm/sup 2/ or more.

The evolution of build-up package technology and its design challenges

Abstract: This paper reviews sequential build-up (SBU) laminate substrate development from its beginning in 1988. It reports on developments in this technology for IBM applications since its adoption in 2000. These laminated substrates are nonuniform structures composed of three elements: a core, build-up layers, and finishing layers. Each element has evolved to meet the demands of packaging applications. Thin-film processing has greatly enhanced the wiring capability of SBU laminate substrates and has made this technology very suitable for high-performance designs. This paper focuses on the challenges encountered by IBM during the design, manufacture, and reliability testing phases of development of SBU substrates as solutions for application-specific integrated circuit (ASIC) and microprocessor packaging applications.

Spatially-resolved imaging of microprocessor power (SIMP): hotspots in microprocessors

Abstract: In this paper we present the details of a new technique, which allows for spatially-resolved imaging of microprocessor power (SIMP) under full operational conditions. The method involves two steps: In the first step it utilizes infra-red (IR) thermal imaging, while an IR-transparent coolant flows through a specially designed cooling cell directly over the microprocessor. In the second step the underlying power distribution is derived by determining the temperature fields for each individual power source on the chip. The measured chip temperature distribution is then represented as a superposition of these temperature fields. The SIMP data reveals significant temporal and spatial variations of the microprocessor power/temperature distribution, which can be attributed to the circuit layout as well as to the varying utilization levels across the processor while running real workloads. More specifically, strong non-uniformities or hotspots in the microprocessor power distributions are observed, which have significant implications for packaging and cooling designs.

Semiconductor device, and manufacturing method thereof

Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Brownian-motion-based convective-conductive model for the effective thermal conductivity of nanofluids

Abstract: Here we show through an order-of-magnitude analysis that the enhancement in the effective thermal conductivity of nanofluids is due mainly to the localized convection caused by the Brownian movement of the nanoparticles. We also introduce a convective-conductive model which accurately captures the effects of particle size, choice of base liquid, thermal interfacial resistance between the particles and liquid, temperature, etc. This model is a combination of the Maxwell-Garnett (MG) conduction model and the convection caused by the Brownian movement of the nanoparficles, and reduces to the MG model for large particle sizes. The model is in good agreement with data on water, ethylene glycol, and oil-based nanofluids, and shows that the lighter the nanoparticles, the greater the convection effect in the liquid, regardless of the thermal conductivity of the nanoparticles.

State of the Art of High Heat Flux Cooling Technologies

Abstract: The purpose of this literature review is to compare different cooling technologies currently in development in research laboratories that are competing to solve the challenge of cooling the next generation of high heat flux computer chips. Today, most development efforts are focused on three technologies: liquid cooling in copper or silicon micro-geometry heat dissipation elements, impingement of liquid jets directly on the silicon surface of the chip, and two-phase flow boiling in copper heat dissipation elements or plates with numerous microchannels. The principal challenge is to dissipate the high heat fluxes (current objective is 300 W/cm2) while maintaining the chip temperature below the targeted temperature of 85°C, while of second importance is how to predict the heat transfer coefficients and pressure drops of the cooling process. In this study, the state of the art of these three technologies from recent experimental articles (since 2003) is analyzed and a comparison of the respective merits and ...

High-throughput silicon nanophotonic wavelength-insensitive switch for on-chip optical networks

Abstract: Silicon photonics is deemed to be the solution for dense on-chip optical networks. Now, by using cascaded silicon microring resonators, scientists demonstrate an ultracompact switch that is insensitive to wavelength and temperature. The switch also has fast error-free operation in multiple 40-Gbit s−1 optical channels and is suitable for scalable networks.