Jan M. Rabaey

Bio: Jan M. Rabaey is an academic researcher from Shanghai Jiao Tong University. The author has contributed to research in topics: Compiler & Perspective (graphical). The author has an hindex of 5, co-authored 5 publications receiving 1410 citations.

Digital Integrated Circuits

Abstract: Progressive in content and form, this practical book successfully bridges the gap between the circuit perspective and system perspective of digital integrated circuit design. Digital Integrated Circuits maintains a consistent, logical flow of subject matter throughout. Addresses today's most significant and compelling industry topics, including: the impact of interconnect, design for low power, issues in timing and clocking, design methodologies, and the tremendous effect of design automation on the digital design perspective. For readers interested in digital circuit design.

Embedding Mixed-Signal Design in Systems-on-Chip Innovative approaches and new design methodologies are needed to integrate digital, analog and RF components in CMOS systems-on-a-chip smaller than 100 nm.

Abstract: With semiconductor technology feature size scal- ing below 100 nm, mixed-signal design faces some important challenges, caused among others by reduced supply voltages, process variation, and declining intrinsic device gains. Addres- sing these challenges requires innovative solutions, at the technology, circuit, architecture, and design-methodology level. We present some of these solutions, including a struc- tured platform-based design methodology to enable a mean- ingful exploration of the broad design space and to classify potential solutions in terms of the relevant metrics.

IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS Editor-in-Chief

Abstract: The purpose of this special issue is to engage the engineering and scientific communities, particularly the IEEE, in the emerging ‘Organic Electronics’, also commonly known as ‘Printed Electronics’ (PE). The special issue is intended to delineate the state-of-the-art and challenges facing the PE industry, as well as, to present the current activities, solutions, and future work of researchers, both from academia and industry, in this emerging field. Another purpose is to connect the different disciplines embodied in PE, with emphasis on their implications to circuit design – from a circuits and systems perspective. Broadly, PE encompasses five supply chains: (i) Materials; (ii) Processing Equipment/Platforms; (iii) Circuits/Power Source/Display/Memory/Sensors; (iv) System Integration; and (v) Test and Verification. The scope of this special issue virtually covers all these chains with focus on how they, individually or collectively, affect the printed elements and hence the ensuing circuits and systems. Of specific interest, the scope includes the co-design of the different chains with the third chain (Circuits/Power Source/Display/Memory/Sensors); particularly how innovative circuits and systems design may be able to circumvent or at least mitigate the formidable challenges and shortcomings of PE. Both PE-only (fully-printed) and ‘Hybrid Electronics’ (embodying a heterogeneous integration of conventional silicon transistors with printed circuit elements) on flexible substrate, such as PET plastic films, are within the scope of this special issue. However, there is emphasis for full realizations on flexible substrates (PE-only) as this significantly broadens the application space of PE, for instance, as a key technological enabler for the Internet-of-Things. Put simply, the overall scope encompasses all aspects of the multi-disciplinary PE with emphasis in a circuits and systems perspective and includes: a. Provide prevailing and open problems of PE to the engineering and scientific communities, including the circuits and systems and solid-state design communities;

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

Abstract: High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.

Razor: a low-power pipeline based on circuit-level timing speculation

Abstract: With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the more effective and widely used methods for power-aware computing is dynamic voltage scaling (DVS). In order to obtain the maximum power savings from DVS, it is essential to scale the supply voltage as low as possible while ensuring correct operation of the processor. The critical voltage is chosen such that under a worst-case scenario of process and environmental variations, the processor always operates correctly. However, this approach leads to a very conservative supply voltage since such a worst-case combination of different variabilities is very rare. In this paper, we propose a new approach to DVS, called Razor, based on dynamic detection and correction of circuit timing errors. The key idea of Razor is to tune the supply voltage by monitoring the error rate during circuit operation, thereby eliminating the need for voltage margins and exploiting the data dependence of circuit delay. A Razor flip-flop is introduced that double-samples pipeline stage values, once with a fast clock and again with a time-borrowing delayed clock. A metastability-tolerant comparator then validates latch values sampled with the fast clock. In the event of timing error, a modified pipeline mispeculation recovery mechanism restores correct program state. A prototype Razor pipeline was designed in a 0.18 /spl mu/m technology and was analyzed. Razor energy overhead during normal operation is limited to 3.1%. Analyses of a full-custom multiplier and a SPICE-level Kogge-Stone adder model reveal that substantial energy savings are possible for these devices (up to 64.2%) with little impact on performance due to error recovery (less than 3%).

Force-directed scheduling for the behavioral synthesis of ASICs

Abstract: A general scheduling methodology is presented that can be integrated into specialized or general-purpose high-level synthesis systems. An initial version of the force-directed scheduling algorithm at the heart of this methodology was originally presented by the authors in 1987. The latest implementation of the logarithm introduced here reduces the number of functional units, storage units, and buses required by balancing the concurrency of operations assigned to them. The algorithm supports a comprehensive set of constraint types and scheduling modes. These include multicycle and chained operations; mutually exclusive operations; scheduling under fixed global timing constraints with minimization of functional unit costs, minimization of register costs, and minimization of global interconnect requirements; scheduling with local time constraints (on operation pairs); scheduling under fixed hardware resource constraints; functional pipelining; and structural pipeline (use of pipeline functional units). Examples from current literature, one of which was chosen as a benchmark for the 1988 High-Level Synthesis Workshop, are used to illustrate the effectiveness of the approach. >

Low-power logic styles: CMOS versus pass-transistor logic

Abstract: Recently reported logic style comparisons based on full-adder circuits claimed complementary pass-transistor logic (CPL) to be much more power-efficient than complementary CMOS. However, new comparisons performed on more efficient CMOS circuit realizations and a wider range of different logic cells, as well as the use of realistic circuit arrangements demonstrate CMOS to be superior to CPL in most cases with respect to speed, area, power dissipation, and power-delay products. An implemented 32-b adder using complementary CMOS has a power-delay product of less than half that of the CPL version. Robustness with respect to voltage scaling and transistor sizing, as well as generality and ease-of-use, are additional advantages of CMOS logic gates, especially when cell-based design and logic synthesis are targeted. This paper shows that complementary CMOS is the logic style of choice for the implementation of arbitrary combinational circuits if low voltage, low power, and small power-delay products are of concern.

Energy-Optimal Mobile Cloud Computing under Stochastic Wireless Channel

Abstract: This paper provides a theoretical framework of energy-optimal mobile cloud computing under stochastic wireless channel. Our objective is to conserve energy for the mobile device, by optimally executing mobile applications in the mobile device (i.e., mobile execution) or offloading to the cloud (i.e., cloud execution). One can, in the former case sequentially reconfigure the CPU frequency; or in the latter case dynamically vary the data transmission rate to the cloud, in response to the stochastic channel condition. We formulate both scheduling problems as constrained optimization problems, and obtain closed-form solutions for optimal scheduling policies. Furthermore, for the energy-optimal execution strategy of applications with small output data (e.g., CloudAV), we derive a threshold policy, which states that the data consumption rate, defined as the ratio between the data size (L) and the delay constraint (T), is compared to a threshold which depends on both the energy consumption model and the wireless channel model. Finally, numerical results suggest that a significant amount of energy can be saved for the mobile device by optimally offloading mobile applications to the cloud in some cases. Our theoretical framework and numerical investigations will shed lights on system implementation of mobile cloud computing under stochastic wireless channel.