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Janak H. Patel

Researcher at University of Illinois at Urbana–Champaign

Publications -  168
Citations -  9261

Janak H. Patel is an academic researcher from University of Illinois at Urbana–Champaign. The author has contributed to research in topics: Automatic test pattern generation & Fault coverage. The author has an hindex of 48, co-authored 168 publications receiving 9113 citations. Previous affiliations of Janak H. Patel include University of Manchester & Royal Free Hospital.

Papers
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Proceedings ArticleDOI

HITEC: a test generation package for sequential circuits

TL;DR: HITEC is presented, a sequential circuit test generation package to generate test patterns for sequential circuits, without assuming the use of scan techniques or a reset state, and several new techniques are introduced to improve the performance of test generation.
Proceedings ArticleDOI

A low-overhead coherence solution for multiprocessors with private cache memories

TL;DR: This paper presents a cache coherence solution for multiprocessors organized around a single time-shared bus that aims at reducing bus traffic and hence bus wait time and increases the overall processor utilization.
Proceedings ArticleDOI

Test set compaction algorithms for combinational circuits

TL;DR: In this paper, two new algorithms, redundant vector elimination (RVE) and essential fault reduction (EFR), were proposed for generating compact test sets for combinational circuits under the single stuck at fault model.
Journal Article

Guidance for control of infections with carbapenem-resistant or carbapenemase-producing Enterobacteriaceae in acute care facilities.

TL;DR: In this paper, the authors provide updated recommendations from CDC and the Healthcare Infection Control Practices Advisory Committee (HICPAC) for the control of CRE or carbapenemase-producing Enterobacteriaceae in acute care (inpatient) facilities.
Proceedings ArticleDOI

Reducing test application time for full scan embedded cores

TL;DR: In this article, the authors proposed a parallel serial full scan (PSFS) technique for reducing the test application time for full scan embedded cores, which divides the scan chain into multiple partitions and shifts in the same vector to each scan chain through a single scan in input.