J
Janakiraman Viraraghavan
Researcher at Indian Institute of Technology Madras
Publications - 18
Citations - 91
Janakiraman Viraraghavan is an academic researcher from Indian Institute of Technology Madras. The author has contributed to research in topics: Logic gate & Transistor. The author has an hindex of 6, co-authored 16 publications receiving 80 citations. Previous affiliations of Janakiraman Viraraghavan include Indian Institute of Science & IBM.
Papers
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Journal ArticleDOI
A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access
Gregory J. Fredeman,Donald W. Plass,Abraham Mathews,Janakiraman Viraraghavan,Kenneth J. Reyer,Thomas J. Knips,Thomas R. Miller,Elizabeth L. Gerhard,Dinesh Kannambadi,Chris Paone,Dongho Lee,Daniel J. Rainey,Michael A. Sperling,Michael Whalen,Steven Burns,Rajesh R. Tummuru,Herbert L. Ho,Alberto Cestero,Norbert Arnold,Babar A. Khan,Toshiaki Kirihata,Subramanian S. Iyer +21 more
TL;DR: A 1.1 Mb embedded DRAM macro (eDRAM), for next-generation IBM SOI processors, employs 14 nm FinFET logic technology with 0.0174 μm2 deep-trench capacitor cell that enables a high voltage gain of a power-gated inverter at mid-level input voltage.
Journal ArticleDOI
80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity
Balaji Jayaraman,Derek H. Leu,Janakiraman Viraraghavan,Alberto Cestero,Ming Yin,John Golz,Rajesh R. Tummuru,Ramesh Raghavan,Dan Moy,Thejas Kempanna,Faraz Khan,Toshiaki Kirihata,Subramanian S. Iyer +12 more
TL;DR: The design and implementation of an 80-kb logic-embedded non-volatile multi-time programmable memory (MTPM) with no added process complexity is described and high-temperature stress results show a projected data retention of 10 years at 125 °C.
Proceedings ArticleDOI
80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity
Janakiraman Viraraghavan,Derek H. Leu,Balaji Jayaraman,Alberto Cestero,Robert E. Kilker,Ming Yin,John Golz,Rajesh R. Tummuru,Ramesh Raghavan,Dan Moy,Thejas Kempanna,Faraz Khan,Toshiaki Kirihata,Subramanian S. Iyer +13 more
TL;DR: An 80Kb logic Embedded Multi-Time Programmable Memory (MTPM) employs charge trapping and de-trapping behavior in 32nm/22nm High-K transistor, resulting in no added process complexity.
Journal ArticleDOI
Statistical Compact Model Extraction: A Neural Network Approach
TL;DR: ANNs can model a much higher degree of nonlinearity compared to existing quadratic polynomial models and, hence, can even be used in sub-100-nm technologies to model leakage current that exponentially depends on process parameters.
Proceedings ArticleDOI
Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization
TL;DR: This work characterize standard cell libraries for statistical leakage analysis based on models for transistor stacks and investigates the use of neural networks for the combined PVT model, for the stacks, which can capture the effect of inter die, intra gate variations, supply voltage and temperature on leakage.