Janakiraman Viraraghavan

Bio: Janakiraman Viraraghavan is an academic researcher from Indian Institute of Technology Madras. The author has contributed to research in topics: Logic gate & Transistor. The author has an hindex of 6, co-authored 16 publications receiving 80 citations. Previous affiliations of Janakiraman Viraraghavan include Indian Institute of Science & IBM.

Test method and structure for integrated circuits before complete metalization

Abstract: Aspects of the present disclosure include methods and test structures for an intermediate metal level of an integrated circuit (IC). A method according to the present disclosure can include: fabricating a first plurality of metal levels including an intermediate metal level of an IC structure, the intermediate metal level being one of a plurality of metal levels in the IC structure other than a capping metal level of the IC structure; performing a first functional test on a first circuit positioned within the intermediate metal level; fabricating a second plurality of metal levels after performing the first functional test, the second plurality of metal levels including the capping metal level of the IC structure; and performing a second functional test on a second circuit positioned within the plurality of metal levels, after the fabricating of the capping metal level.

Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks

Abstract: We propose a logic gate leakage model based on transistor stacks, which includes local transistor level process variation parameters along with global process variation parameters and supply and temperature The stack models include both subthreshold as well as gate leakage and consider the input vector state We examine cells from an industrial standard cell library and find that most cells can be modeled with simple stacks, which have a linear chain of transistors However some gates like XOR, Majority or Muxes need complex stacks and we show how these can be modeled Our experiments show that only 18 different stack models are needed to predict the leakage of all gates in this industrial library Re-use of the same models for pass transistor logic circuits and multi-finger transistors is also demonstrated We explicitly include voltage and temperature into the models to support joint estimation of power supply IR drops and leakage currents, as well as enable analysis for dynamic voltage scaling applications We use artificial neural networks to create unified models which include global and local process variations, supply voltage in the range of V DD /2- V DD and temperature in the range 0-100 °C These models are very useful for performing statistical leakage analysis of large circuits Results from the ISCAS'85 benchmark circuits show that neural network based stack models can predict the PDF of leakage current of large circuits across supply voltage and temperature accurately with the average error in mean being less than 2% and that in standard deviation being less than 7% when compared to SPICE Further gate level validation has been done for both an industrial 130 nm and 45 nm PTM model files

Layout-Based Digital IC Course Projects in Large Classes: Implementation, Evaluation, and Plagiarism Detection

Abstract: Contribution: The ability to design circuit layouts is a critical component of circuit design. This article presents an approach wherein layout-based design projects can be integrated into the traditional digital integrated circuit (IC) curriculum targeted at large classes and addresses the relevant challenges. Background: Most circuit design curricula cover aspects of layout design and good layout design practices in some detail, but the actual assignment of layout design is done only in classes with restricted sizes due to various factors, including the lack of propriety software, evaluation, or plagiarism detection strategies. Intended Outcomes: To be able to integrate layout-based design projects into the digital IC curriculum targeting large classes. Application Design: Freely available and opensource tools were used for the projects. Additional tool features were repurposed for plagiarism detection. Findings: Feedback collected from the students and quiz performance indicate a marked increase in meeting the learning objectives with the inclusion of layout-based projects. The proposed plagiarism detection strategy successfully identified instances of plagiarism.

Dual-bit 3-t high density mtprom array and method of operation thereof

Abstract: A multi-time programmable memory (MTPM) memory cell and method of operating Each MTPM bit cell including a first FET transistor and a second FET transistor having a first common connection, and said second FET transistor and a third FET transistor having a second common connection, said first and second connected FET transistors programmable to store a first bit value, and said second FET and said third connected FET transistors programmable to store a second bit value, wherein said first FET transistor exhibits a low threshold voltage value (LVT), said second FET transistor exhibits an elevated threshold voltage value HVT and said third FET transistor exhibits a threshold value LVT lower than HVT The MTPM cell enables two bits of information to be stored as default bit values like an electrical fuse To store opposite bit values, the LVT transistors are programmed such that their threshold voltage is higher than that of HVT

Flash Based In-Memory Multiply-Accumulate Realisation: A Theoretical Study

Abstract: In memory computing is gaining traction as a technique to implement the Multiply Accumulate (MAC) operation on edge network devices, to perform neural network inference while reducing energy expended in memory-fetch. The voltage developed along a bit-line is an analog representation of the MAC value and needs to be digitized for further processing. In this paper we propose to use the Sense Amp as a comparator to perform the digitization using a serial flash, implemented in memory. Flash ADCs require an ordered set of reference voltages to compare against the input to be digitized. Recognizing that the MAC value is non-uniformly distributed and is application specific we propose an algorithm to generate the reference voltages tailored to the MAC distribution function. Further, we show that the reference voltage can be generated in much the same way as the MAC voltage is generated along a column, in-memory. We provide an algorithm to populate the bit-cells of the reference column to generate the appropriate reference voltage. Experiments on the MNIST, SVHN and CIFAR-10 data sets show that the proposed technique results in a worst case accuracy reduction of 0.8% compared to the Double-Precision evaluation.

DRISA: a DRAM-based Reconfigurable In-Situ Accelerator

Abstract: Data movement between the processing units and the memory in traditional von Neumann architecture is creating the “memory wall” problem. To bridge the gap, two approaches, the memory-rich processor (more on-chip memory) and the compute-capable memory (processing-in-memory) have been studied. However, the first one has strong computing capability but limited memory capacity/bandwidth, whereas the second one is the exact the opposite.To address the challenge, we propose DRISA, a DRAM-based Reconfigurable In-Situ Accelerator architecture, to provide both powerful computing capability and large memory capacity/bandwidth. DRISA is primarily composed of DRAM memory arrays, in which every memory bitline can perform bitwise Boolean logic operations (such as NOR). DRISA can be reconfigured to compute various functions with the combination of the functionally complete Boolean logic operations and the proposed hierarchical internal data movement designs. We further optimize DRISA to achieve high performance by simultaneously activating multiple rows and subarrays to provide massive parallelism, unblocking the internal data movement bottlenecks, and optimizing activation latency and energy. We explore four design options and present a comprehensive case study to demonstrate significant acceleration of convolutional neural networks. The experimental results show that DRISA can achieve 8.8× speedup and 1.2× better energy efficiency compared with ASICs, and 7.7× speedup and 15× better energy efficiency over GPUs with integer operations.CCS CONCEPTS• Hardware → Dynamic memory; • Computer systems organization → reconfigurable computing; Neural networks;

Enabling scientific computing on memristive accelerators

Abstract: Linear algebra is ubiquitous across virtually every field of science and engineering, from climate modeling to macroeconomics. This ubiquity makes linear algebra a prime candidate for hardware acceleration, which can improve both the run time and the energy efficiency of a wide range of scientific applications. Recent work on memristive hardware accelerators shows significant potential to speed up matrix-vector multiplication (MVM), a critical linear algebra kernel at the heart of neural network inference tasks. Regrettably, the proposed hardware is constrained to a narrow range of workloads: although the eight- to 16-bit computations afforded by memristive MVM accelerators are acceptable for machine learning, they are insufficient for scientific computing where high-precision floating point is the norm. This paper presents the first proposal to enable scientific computing on memristive crossbars. Three techniques are explored---reducing overheads by exploiting exponent range locality, early termination of fixed-point computation, and static operation scheduling---that together enable a fixed-point memristive accelerator to perform high-precision floating point without the exorbitant cost of naive floating-point emulation on fixed-point hardware. A heterogeneous collection of crossbars with varying sizes is proposed to efficiently handle sparse matrices, and an algorithm for mapping the dense subblocks of a sparse matrix to an appropriate set of crossbars is investigated. The accelerator can be combined with existing GPU-based systems to handle datasets that cannot be efficiently handled by the memristive accelerator alone. The proposed optimizations permit the memristive MVM concept to be applied to a wide range of problem domains, respectively improving the execution time and energy dissipation of sparse linear solvers by 10.3x and 10.9x over a purely GPU-based system.

Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High- $k$ -Metal-Gate CMOS Technologies

Abstract: The availability of on-chip non-volatile memory for advanced high- $k$ -metal-gate CMOS technology nodes has been limited due to integration and scaling challenges as well as operational voltage incompatibilities, while its need continues to grow rapidly in modern high-performance systems. By exploiting intrinsic device self-heating enhanced charge trapping in as fabricated high- $k$ -metal-gate logic devices, we introduce a unique multiple-time programmable embedded non-volatile memory element, called the ‘charge trap transistor’ (CTT), for high- $k$ -metal-gate CMOS technologies. Functionality and feasibility of using CTT memory devices have been demonstrated on 22 nm planar and 14 nm FinFET technology platforms, including fully functional product prototype memory arrays. These transistor memory devices offer high density ( $\sim 0.144\mu\mathrm{m}^{2}$ /bit for 22 nm and $\sim 0.082\mu\mathrm{m}^{2}$ /bit for 14 nm technology), logic voltage compatible and low peak power operation (~4mW), and excellent retention for a fully integrated and scalable embedded non-volatile memory without added process complexity or masks.

Prediction of Process Variation Effect for Ultrascaled GAA Vertical FET Devices Using a Machine Learning Approach

Abstract: In this brief, we present an accurate and efficient machine learning (ML) approach which predicts variations in key electrical parameters using process variations (PVs) from ultrascaled gate-all-around (GAA) vertical FET (VFET) devices. The 3-D stochastic TCAD simulation is the most powerful tool for analyzing PVs, but for ultrascaled devices, the computation cost is too high because this method requires simultaneous analysis of various factors. The proposed ML approach is a new method which predicts the effects of the variability sources of ultrascaled devices. It also shows the same degree of accuracy, as well as improved efficiency compared to a 3-D stochastic TCAD simulation. An artificial neural network (ANN)-based ML algorithm can make multi-input -multi-output (MIMO) predictions very effectively and uses an internal algorithm structure that is improved relative to existing techniques to capture the effects of PVs accurately. This algorithm incurs approximately 16% of the computation cost by predicting the effects of process variability sources with less than 1% error compared to a 3-D stochastic TCAD simulation.

Radiation Effects in Advanced and Emerging Nonvolatile Memories

Abstract: Despite hitting major roadblocks in 2-D scaling, NAND flash continues to scale in the vertical direction and dominate the commercial nonvolatile memory market. However, several emerging nonvolatile technologies are under development by major commercial foundries or are already in small volume production, motivated by storage-class memory and embedded application drivers. These include spin-transfer torque magnetic random access memory (STT-MRAM), resistive random access memory (ReRAM), phase change random access memory (PCRAM), and conductive bridge random access memory (CBRAM). Emerging memories have improved resilience to radiation effects compared to flash, which is based on storing charge, and hence may offer an expanded selection from which radiation-tolerant system designers can choose from in the future. This review discusses the material and device physics, fabrication, operational principles, and commercial status of scaled 2-D flash, 3-D flash, and emerging memory technologies. Radiation effects relevant to each of these memories are described, including the physics of and errors caused by total ionizing dose, displacement damage, and single-event effects, with an eye toward the future role of emerging technologies in radiation environments.