Janakiraman Viraraghavan

Bio: Janakiraman Viraraghavan is an academic researcher from Indian Institute of Technology Madras. The author has contributed to research in topics: Logic gate & Transistor. The author has an hindex of 6, co-authored 16 publications receiving 80 citations. Previous affiliations of Janakiraman Viraraghavan include Indian Institute of Science & IBM.

Geometric Programming Approach to Glitch Minimization via Gate Sizing

Abstract: The problem of gate sizing to meet timing specification while minimizing functional power/area is well understood and is solved by the use of geometric programs (GPs). While these area minimization GP (AM-GP) formulations minimize functional power, they do not address the problem of glitches. Glitches are extraneous transitions caused by signal arrival time imbalance at the input nodes of logic gates. A gate sizing algorithm, area-glitch minimization GP (AGM-GP), is proposed to reduce glitches while constraining area and adhering to a timing specification. Glitch reduction is achieved through signal arrival time balancing posed as posynomials in a GP formulation. Prior art does not exploit the complete power of gate sizing when reducing glitches in an attempt to meet the timing specification. In particular, the proposed formulation allows both upsizing and downsizing without causing any timing violation, at the expense of a marginal increase in area. Traditional downsizing methods can be used to further reduce glitches over and above the AGM-GP solution. Simulation results on the ISCAS-85 benchmark circuits show an overall reduction of 20.4% glitch power and 9.5% total power which is, respectively, 13.8% and 3.9% better than just downsizing the AM-GP solution. This power reduction was achieved with an average area increase of 4.2%.

An Area-Efficient Word-Line Pitch-Aligned 8T SRAM Compatible Digital-to-Analog Converter

Abstract: Area and energy-efficient data converters are an integral part of In-Memory Compute (IMC) engines. The conventional Digital to Analog Converters (DACs) uses binary-weighted pull-up current sources with scan-flops feeding in the digital input. These bulky pull-up devices and scan-flops make it hard to integrate along-side a memory array in an area-efficient manner. Further, it is prone to error due to local variations owing to limited digital control. In this paper, we propose an area-efficient, Word-Line (WL) pitch-aligned, layout friendly InMemory compatible DAC (IM-DAC), whose layout resembles the 8T SRAM array very closely, thus achieving memory array-like density. Simulation results show that the worst-case INL and DNL is 2.42 LSB and -0.32 LSB, respectively. We obtained a 3.4X area advantage in comparison with the conventional DAC. The high-density layout allows for additional calibration pull-up stacks, with minimal area penalty, that reduces the standard deviation of the linearized-current to 48.76% of the corresponding value before calibration.

Distributed current source/sink using inactive memory elements

Abstract: A Multi-Time-Programmable-Memory (MTPM) array architecture, whose structure comprising of having Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) memory elements arranged in a set of twin-pairs coupled by wordlines (WLs), bitlines (BLs) and sourcelines (SLs). More specifically, the use of inactive portions of the MTPM array structure as substitutes for conventional BL write driver areas by utilizing a set of twin-pairs acting in parallel. These substituted twin-pair sets will improve programming efficiency (VGS) and retention (VDS) through a lowering Interconnect (IR) drop and VDS drops at the BL write driver.

DRISA: a DRAM-based Reconfigurable In-Situ Accelerator

Abstract: Data movement between the processing units and the memory in traditional von Neumann architecture is creating the “memory wall” problem. To bridge the gap, two approaches, the memory-rich processor (more on-chip memory) and the compute-capable memory (processing-in-memory) have been studied. However, the first one has strong computing capability but limited memory capacity/bandwidth, whereas the second one is the exact the opposite.To address the challenge, we propose DRISA, a DRAM-based Reconfigurable In-Situ Accelerator architecture, to provide both powerful computing capability and large memory capacity/bandwidth. DRISA is primarily composed of DRAM memory arrays, in which every memory bitline can perform bitwise Boolean logic operations (such as NOR). DRISA can be reconfigured to compute various functions with the combination of the functionally complete Boolean logic operations and the proposed hierarchical internal data movement designs. We further optimize DRISA to achieve high performance by simultaneously activating multiple rows and subarrays to provide massive parallelism, unblocking the internal data movement bottlenecks, and optimizing activation latency and energy. We explore four design options and present a comprehensive case study to demonstrate significant acceleration of convolutional neural networks. The experimental results show that DRISA can achieve 8.8× speedup and 1.2× better energy efficiency compared with ASICs, and 7.7× speedup and 15× better energy efficiency over GPUs with integer operations.CCS CONCEPTS• Hardware → Dynamic memory; • Computer systems organization → reconfigurable computing; Neural networks;

Enabling scientific computing on memristive accelerators

Abstract: Linear algebra is ubiquitous across virtually every field of science and engineering, from climate modeling to macroeconomics. This ubiquity makes linear algebra a prime candidate for hardware acceleration, which can improve both the run time and the energy efficiency of a wide range of scientific applications. Recent work on memristive hardware accelerators shows significant potential to speed up matrix-vector multiplication (MVM), a critical linear algebra kernel at the heart of neural network inference tasks. Regrettably, the proposed hardware is constrained to a narrow range of workloads: although the eight- to 16-bit computations afforded by memristive MVM accelerators are acceptable for machine learning, they are insufficient for scientific computing where high-precision floating point is the norm. This paper presents the first proposal to enable scientific computing on memristive crossbars. Three techniques are explored---reducing overheads by exploiting exponent range locality, early termination of fixed-point computation, and static operation scheduling---that together enable a fixed-point memristive accelerator to perform high-precision floating point without the exorbitant cost of naive floating-point emulation on fixed-point hardware. A heterogeneous collection of crossbars with varying sizes is proposed to efficiently handle sparse matrices, and an algorithm for mapping the dense subblocks of a sparse matrix to an appropriate set of crossbars is investigated. The accelerator can be combined with existing GPU-based systems to handle datasets that cannot be efficiently handled by the memristive accelerator alone. The proposed optimizations permit the memristive MVM concept to be applied to a wide range of problem domains, respectively improving the execution time and energy dissipation of sparse linear solvers by 10.3x and 10.9x over a purely GPU-based system.

Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High- $k$ -Metal-Gate CMOS Technologies

Abstract: The availability of on-chip non-volatile memory for advanced high- $k$ -metal-gate CMOS technology nodes has been limited due to integration and scaling challenges as well as operational voltage incompatibilities, while its need continues to grow rapidly in modern high-performance systems. By exploiting intrinsic device self-heating enhanced charge trapping in as fabricated high- $k$ -metal-gate logic devices, we introduce a unique multiple-time programmable embedded non-volatile memory element, called the ‘charge trap transistor’ (CTT), for high- $k$ -metal-gate CMOS technologies. Functionality and feasibility of using CTT memory devices have been demonstrated on 22 nm planar and 14 nm FinFET technology platforms, including fully functional product prototype memory arrays. These transistor memory devices offer high density ( $\sim 0.144\mu\mathrm{m}^{2}$ /bit for 22 nm and $\sim 0.082\mu\mathrm{m}^{2}$ /bit for 14 nm technology), logic voltage compatible and low peak power operation (~4mW), and excellent retention for a fully integrated and scalable embedded non-volatile memory without added process complexity or masks.

Prediction of Process Variation Effect for Ultrascaled GAA Vertical FET Devices Using a Machine Learning Approach

Abstract: In this brief, we present an accurate and efficient machine learning (ML) approach which predicts variations in key electrical parameters using process variations (PVs) from ultrascaled gate-all-around (GAA) vertical FET (VFET) devices. The 3-D stochastic TCAD simulation is the most powerful tool for analyzing PVs, but for ultrascaled devices, the computation cost is too high because this method requires simultaneous analysis of various factors. The proposed ML approach is a new method which predicts the effects of the variability sources of ultrascaled devices. It also shows the same degree of accuracy, as well as improved efficiency compared to a 3-D stochastic TCAD simulation. An artificial neural network (ANN)-based ML algorithm can make multi-input -multi-output (MIMO) predictions very effectively and uses an internal algorithm structure that is improved relative to existing techniques to capture the effects of PVs accurately. This algorithm incurs approximately 16% of the computation cost by predicting the effects of process variability sources with less than 1% error compared to a 3-D stochastic TCAD simulation.

Radiation Effects in Advanced and Emerging Nonvolatile Memories

Abstract: Despite hitting major roadblocks in 2-D scaling, NAND flash continues to scale in the vertical direction and dominate the commercial nonvolatile memory market. However, several emerging nonvolatile technologies are under development by major commercial foundries or are already in small volume production, motivated by storage-class memory and embedded application drivers. These include spin-transfer torque magnetic random access memory (STT-MRAM), resistive random access memory (ReRAM), phase change random access memory (PCRAM), and conductive bridge random access memory (CBRAM). Emerging memories have improved resilience to radiation effects compared to flash, which is based on storing charge, and hence may offer an expanded selection from which radiation-tolerant system designers can choose from in the future. This review discusses the material and device physics, fabrication, operational principles, and commercial status of scaled 2-D flash, 3-D flash, and emerging memory technologies. Radiation effects relevant to each of these memories are described, including the physics of and errors caused by total ionizing dose, displacement damage, and single-event effects, with an eye toward the future role of emerging technologies in radiation environments.