Janet Hopkins

Bio: Janet Hopkins is an academic researcher. The author has contributed to research in topics: Etching (microfabrication) & Dry etching. The author has an hindex of 11, co-authored 27 publications receiving 966 citations.

Method of surface treatment of semiconductor substrates

Abstract: This invention relates to methods for treatment of semiconductor substrates and in particular a method of etching a trench in a semiconductor substrate in a reactor chamber using alternatively reactive ion etching and depositing a passivation layer by chemical vapour deposition, wherein one or more of the following parameters: gas flow rates, chamber pressure, plasma power, substrate bias, etch rate, deposition rate, cycle time and etching/deposition ratio vary with time.

Recent advances in silicon etching for MEMS using the ASE™ process

Abstract: In the ongoing enhancement of MEMS applications, the STS Advanced Silicon Etch, ASE™, process satisfies the demanding requirements of the industry. Typically, highly anisotropic, high aspect ratios profiles with fine CD control are required. Selectivities to photoresist of 150:1 with Si etch rates of up to 7 μm/min are achievable. Applications range from shallow etched optical devices to through wafer membrane etches. This paper details some of the fundamental trends of the ASE™ process and goes on to discuss how the process has been enhanced to meet product specifications. Parameter ramping is a powerful technique used to achieve the often conflicting requirements of high etch rate with good profile/CD control. The results are presented in this paper.

Silicon micromachining using a high-density plasma source

Abstract: Dry etching of Si is critical in satisfying the demands of the micromachining industry. The micro-electro-mechanical systems (MEMS) community requires etches capable of high aspect ratios, vertical profiles, good feature size control and etch uniformity along with high throughput to satisfy production requirements. Surface technology systems' (STS's) high-density inductively coupled plasma (ICP) etch tool enables a wide range of applications to be realized whilst optimizing the above parameters. Components manufactured from Si using an STS ICP include accelerometers and gyroscopes for military, automotive and domestic applications. STS's advanced silicon etch (ASETM) has also allowed the first generation of MEMS-based optical switches and attenuators to reach the marketplace. In addition, a specialized application for fabricating the next generation photolithography exposure masks has been optimized for 200 mm diameter wafers, to depths of ~750 µm. Where the profile is not critical, etch rates of greater than 8 µm min-1 have been realized to replace previous methods such as wet etching. This is also the case for printer applications. Specialized applications that require etching down to pyrex or oxide often result in the loss of feature size control at the interface; this is an industry wide problem. STS have developed a technique to address this. The rapid progression of the industry has led to development of the STS ICP etch tool, as well as the process.

A method and apparatus for etching a substrate

Abstract: There is disclosed a method and apparatus for etching a substrate. The method comprises the steps of etching a substrate or alternately etching and depositing a passivation layer. A bias frequency, which may be pulsed, may be applied to the substrate and may be at or below the ion plasma frequency.

The Benefits of Process Parameter Ramping During The Plasma Etching of High Aspect Ratio Silicon Structures

Abstract: In the ongoing enhancement of MEMS applications, the STS Advanced Silicon Etch, (ASETM). process satisfies the demanding requirements of the industry. Typically, highly anisotropic. high aspect ratios profiles with fine CD (critical dimension) control are required. Selectivities to photoresist of 150:1 with Si etch rates of up to 10μm/min are demonstrated. Applications range from shallow etched optical devices to through wafer membrane etches. This paper details some of the fundamental trends of the ASETM process and goes on to discuss how the process has been enhanced to meet product specifications. Parameter ramping is a powerful technique used to achieve the often-conflicting requirements of high etch rate with good profile/CD control. The results are presented in this paper.

Etch rates for micromachining processing-Part II

Abstract: Samples of 53 materials that are used or potentially can be used or in the fabrication of microelectromechanical systems and integrated circuits were prepared: single-crystal silicon with two doping levels, polycrystalline silicon with two doping levels, polycrystalline germanium, polycrystalline SiGe, graphite, fused quartz, Pyrex 7740, nine other preparations of silicon dioxide, four preparations of silicon nitride, sapphire, two preparations of aluminum oxide, aluminum, Al/2%Si, titanium, vanadium, niobium, two preparations of tantalum, two preparations of chromium, Cr on Au, molybdenum, tungsten, nickel, palladium, platinum, copper, silver, gold, 10 Ti/90 W, 80 Ni/20 Cr, TiN, four types of photoresist, resist pen, Parylene-C, and spin-on polyimide. Selected samples were etched in 35 different etches: isotropic silicon etchant, potassium hydroxide, 10:1 HF, 5:1 BHF, Pad Etch 4, hot phosphoric acid, Aluminum Etchant Type A, titanium wet etchant, CR-7 chromium etchant, CR-14 chromium etchant, molybdenum etchant, warm hydrogen peroxide, Copper Etchant Type CE-200, Copper Etchant APS 100, dilute aqua regia, AU-5 gold etchant, Nichrome Etchant TFN, hot sulfuric+phosphoric acids, Piranha, Microstrip 2001, acetone, methanol, isopropanol, xenon difluoride, HF+H/sub 2/O vapor, oxygen plasma, two deep reactive ion etch recipes with two different types of wafer clamping, SF/sub 6/ plasma, SF/sub 6/+O/sub 2/ plasma, CF/sub 4/ plasma, CF/sub 4/+O/sub 2/ plasma, and argon ion milling. The etch rates of 620 combinations of these were measured. The etch rates of thermal oxide in different dilutions of HF and BHF are also reported. Sample preparation and information about the etches is given.

High aspect ratio silicon etch: A review

Abstract: High aspect ratio (HAR) silicon etch is reviewed, including commonly used terms, history, main applications, different technological methods, critical challenges, and main theories of the technologies. Chronologically, HAR silicon etch has been conducted using wet etch in solution, reactive ion etch (RIE) in low density plasma, single-step etch at cryogenic conditions in inductively coupled plasma (ICP) combined with RIE, time-multiplexed deep silicon etch in ICP-RIE configuration reactor, and single-step etch in high density plasma at room or near room temperature. Key specifications are HAR, high etch rate, good trench sidewall profile with smooth surface, low aspect ratio dependent etch, and low etch loading effects. Till now, time-multiplexed etch process is a popular industrial practice but the intrinsic scalloped profile of a time-multiplexed etch process, resulting from alternating between passivation and etch, poses a challenge. Previously, HAR silicon etch was an application associated primarily with microelectromechanical systems. In recent years, through-silicon-via (TSV) etch applications for three-dimensional integrated circuit stacking technology has spurred research and development of this enabling technology. This potential large scale application requires HAR etch with high and stable throughput, controllable profile and surface properties, and low costs.

Plasma etching: Yesterday, today, and tomorrow

Abstract: The field of plasma etching is reviewed. Plasma etching, a revolutionary extension of the technique of physical sputtering, was introduced to integrated circuit manufacturing as early as the mid 1960s and more widely in the early 1970s, in an effort to reduce liquid waste disposal in manufacturing and achieve selectivities that were difficult to obtain with wet chemistry. Quickly, the ability to anisotropically etch silicon, aluminum, and silicon dioxide in plasmas became the breakthrough that allowed the features in integrated circuits to continue to shrink over the next 40 years. Some of this early history is reviewed, and a discussion of the evolution in plasma reactor design is included. Some basic principles related to plasma etching such as evaporation rates and Langmuir–Hinshelwood adsorption are introduced. Etching mechanisms of selected materials, silicon, silicon dioxide, and low dielectric-constant materials are discussed in detail. A detailed treatment is presented of applications in current silicon integrated circuit fabrication. Finally, some predictions are offered for future needs and advances in plasma etching for silicon and nonsilicon-based devices.

From rolling ball to complete wetting: the dynamic tuning of liquids on nanostructured surfaces

Abstract: In this work, for the first time, a dynamic electrical control of the wetting behavior of liquids on nanostructured surfaces, which spans the entire possible range from the superhydrophobic behavior to nearly complete wetting, has been demonstrated. Moreover, this kind of dynamic control was obtained at voltages as low as 22 V. We have demonstrated that the liquid droplet on a nanostructured surface exhibits sharp transitions between three possible wetting states as a function of applied voltage and liquid surface tension. We have examined experimentally and theoretically the nature of these transitions. The reported results provide novel methods of manipulating liquids at the microscale.

Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates

Abstract: A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.