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Jang Kye Lee

Bio: Jang Kye Lee is an academic researcher from Seoul National University. The author has contributed to research in topics: NAND gate & Flash (photography). The author has an hindex of 1, co-authored 1 publications receiving 3 citations.

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Journal ArticleDOI
TL;DR: In this paper , the curvature of the channel was defined as a wave factor (WF) parameter, and simulated 3D NAND device with the WF applied channel was investigated, which showed that degradation of erase characteristic by WF can be prevented by applying thicker blocking oxide.
Abstract: Since the most of three dimensional (3D) NAND devices’ channel is composed of polysilicon grain, the actual 3D NAND channel has a wave-shaped channel, not uniform shape. In this study, we defined the curvature of the channel as a ‘Wave Factor (WF)’ parameter, and simulated 3D NAND device with the WF applied channel. Various effects of the curvature in the channel on the program and erase operation of the device have been investigated. When the channel is wave-shaped, the electric field tends to be concentrated on the corner region of the blocking oxide during the program operation, which causes increase of the electron back tunneling to the gate. Therefore, program speed degraded as the WF value higher. During the erase operation, the same with program operation, the electric field concentrated on the corner of the blocking oxide increased, enhanced electron back tunneling from the metal gate occurred while less amount of hole charge trapped. As a result, $\text{V}_{\mathrm {TH}}$ shift after the erase operation decreased according to increased WF. This phenomenon becomes more serious on the short channel condition. In addition, the result shows that degradation of erase characteristic by WF can be prevented by applying thicker blocking oxide.
Journal ArticleDOI
TL;DR: In this article , a neural network (NN)-applied optimization method was proposed to improve program efficiency for fast NAND cell operation by predicting the threshold voltages of the 21 states of a single NAND flash memory within a second.
Abstract: The enhancement of program efficiency is essential for fast NAND cell operation. However, it is difficult to simultaneously consider many factors, such as structural parameters and trap characteristics, having complex relationships. To overcome these problems, we proposed a neural network (NN)-applied optimization method. First, an optimal network structure was selected by comparing the network performance and learning time. The selected network accurately predicted the threshold voltages of the 21 states of a single NAND cell within a second. Next, an optimization method to improve program efficiency is suggested. The improved NAND cell structure is obtained using a trained NN and numerical method. Here, the optimization required only a few minutes for one optimization process and could consider all parameters simultaneously. Finally, the optimized NAND cell was evaluated using a technology computer-aided design (TCAD) simulation, and its program efficiency was verified. This study shows a specific example of machine learning applied to the semiconductor area, especially in NAND flash memory.
Journal ArticleDOI
TL;DR: A modified 1-D Poisson equation was proposed that shows better accuracy than the existing model by reflecting the spatial distribution of electrons trapped by the program operation of 3D NAND Flash memories.
Abstract: We developed a new compact model for the program operation of 3D NAND Flash memories. A modified 1-D Poisson equation was proposed that shows better accuracy than the existing model by reflecting the spatial distribution of electrons trapped by the program operation. Under various conditions of program voltage (VPGM) and program time (tPGM), the threshold voltage shift (∆Vt ) was extracted by TCAD (Technology Computer-Aided Design) simulation, and we used this data to validate our new model. It also provides validity of the model for program operation in 3D NAND flash memory along with various TCAD analysis data.
Journal ArticleDOI
TL;DR: In this paper , a positive feedback (PF) device-based synaptic devices for reliable binary neural networks (BNNs) is proposed, which has a charge-trap layer by which the turn-on voltage ( Von) of the device can be adjusted by program/erase operations.
Abstract: This work proposes positive feedback (PF) device-based synaptic devices for reliable binary neural networks (BNNs). Due to PF operation, the fabricated PF device shows a high on/off current ratio (2.69 [Formula: see text] 107). The PF device has a charge-trap layer by which the turn-on voltage ( Von) of the device can be adjusted by program/erase operations and a long-term memory function is implemented. Also, due to the steep switching characteristics of the PF device, the conductance becomes tolerant to the retention time and the variation in turn-on voltage. Simulations show that high accuracy (88.44% for CIFAR-10 image classification) can be achieved in hardware-based BNNs using PF devices with these properties as synapses.