Jang Kyu Lee

Bio: Jang Kyu Lee is an academic researcher from Seoul National University. The author has contributed to research in topics: NAND gate & Field-effect transistor. The author has an hindex of 3, co-authored 7 publications receiving 30 citations.

Prediction of Process Variation Effect for Ultrascaled GAA Vertical FET Devices Using a Machine Learning Approach

Abstract: In this brief, we present an accurate and efficient machine learning (ML) approach which predicts variations in key electrical parameters using process variations (PVs) from ultrascaled gate-all-around (GAA) vertical FET (VFET) devices. The 3-D stochastic TCAD simulation is the most powerful tool for analyzing PVs, but for ultrascaled devices, the computation cost is too high because this method requires simultaneous analysis of various factors. The proposed ML approach is a new method which predicts the effects of the variability sources of ultrascaled devices. It also shows the same degree of accuracy, as well as improved efficiency compared to a 3-D stochastic TCAD simulation. An artificial neural network (ANN)-based ML algorithm can make multi-input -multi-output (MIMO) predictions very effectively and uses an internal algorithm structure that is improved relative to existing techniques to capture the effects of PVs accurately. This algorithm incurs approximately 16% of the computation cost by predicting the effects of process variability sources with less than 1% error compared to a 3-D stochastic TCAD simulation.

Variability-Aware Machine Learning Strategy for 3-D NAND Flash Memories

Abstract: This article proposes a variability-aware machine learning (ML) approach that predicts variations in the key electrical parameters of 3-D NAND Flash memories. For the first time, we have verified the accuracy, efficiency, and generality of the predictive impact factor effects of artificial neural network (ANN) algorithm-based ML systems. ANN-based ML algorithms can be very effective in multiple-input and multiple-output (MIMO) predictions. Therefore, changes in the key electrical characteristics of the device caused by various sources of variability are simultaneously and integrally predicted. This algorithm benchmarks 3-D stochastic TCAD simulation, showing a prediction error rate of less than 1%, as well as a calculation cost reduction of over 80%. In addition, the generality of the algorithm is confirmed by predicting the operating characteristics of the 3-D NAND Flash memory with various structural conditions as the number of layers increases.

Investigation of Gate Sidewall Spacer Optimization From OFF-State Leakage Current Perspective in 3-nm Node Device

Abstract: In this paper, the structural and material optimization of gate sidewall spacer in the perspective of OFF-state leakage current was performed in a 3-nm node nanoplate FET (NPFET). Gate-induced drain leakage (GIDL) current, a dominant factor of OFF-state leakage current, and active performance (ON-current, ON/OFF current ratio, and dynamic performance) were co-optimized according to the structural correlation of gate sidewall spacer with other structural components such as gate, source, and drain length. By optimizing the structure for gate and spacer, intrinsic delay was improved by 9.8%, GIDL current was reduced by ~78%, and then on/off current ratio ( ${I}_{\mathrm{\scriptscriptstyle ON}}/{I}_{\mathrm{\scriptscriptstyle OFF}})$ was enhanced by 4.2 times. On-current ( ${I}_{\mathrm{\scriptscriptstyle ON}}$ ) according to contact resistance ( ${R}_{\text {con}}$ ) and dynamic performance was analyzed in relation to source/drain (S/D) and spacer. Consequently, the intrinsic delay was improved by 10% and GIDL current reduced by about 92%, which enhanced ${I}_{\mathrm{\scriptscriptstyle ON}}/{I}_{\mathrm{\scriptscriptstyle OFF}}$ by 7.9 times accordingly. Furthermore, by comparing structural relations between gate spacer and S/D spacer, a better structural optimization method was proposed.

Analysis on Process Variation Effect of 3D NAND Flash Memory Cell through Machine Learning Model

Abstract: We investigated process variation effect of 3D NAND flash memory cell, especially about geometric variation using a machine learning (ML) model. Geometric variability sources impact on variation of device's electrical parameters such as threshold voltage $(\mathbf{V}_{\mathbf{t}})$ , subthreshold swing (SS), transconductance $(\mathbf{g}_{\mathbf{m}})$ and on-current $(\mathbf{I}_{\mathbf{on}})$ . All these data were analyzed with 3D stochastic Technology Computer-Aided Design (TCAD) simulation and trained through ML model, which is composed of artificial neural network (ANN). The model has multi-input and multi-output (MIMO) structure and deep hidden layers to train and predict complex data of process variation. In order to make ML model more accurate, simulation for constructing training data set was carried out with a large number of random unit cells, which are cut from various strings. The completed ML model was tested with random test data set which had not been used for training to prove its accuracy. Through the test process, ML model showed the error of up to 5% and proved the accuracy of prediction.

Methodology to Predict Random Telegraph Noise Induced Threshold Voltage Shift Using Machine Learning

Abstract: We suggest the methodology to predict the distribution of threshold voltage $(V_{t})$ shift caused by random telegraph noise (RTN). Poly-silicon channels were randomized with a single trap and the neural network was modeled to predict RTN trap-induced $(V_{t})$ fluctuation in 3D NAND Flash Memory. 3D Technology Computer-Aided Design (TCAD) simulations were performed in a unit cell to calculate the Vt shift in a 3D vertical channel. Finally, we extract the distribution of $\mathbf{V}_{\mathbf{t}}$ fluctuation using machine learning.

Outage Probability Performance Analysis and Prediction for Mobile IoV Networks Based on ICS-BP Neural Network

Abstract: In the field of transportation, the Internet of Vehicles (IoV) is an important component of the Internet of Things. The vehicle-to-vehicle communication is particularly challenging in mobile IoV networks because they are operated in complex and highly variable environments. The mobile IoV transmission interruption level can be evaluated by the outage probability (OP) performance. If the OP performance can be analyzed and predicted accurately, the Quality of Service (QoS) in the mobile IoV networks can be improved. However, the analysis and prediction of mobile IoV transmission channels is very challenging because they are highly dynamic. In this article, the analysis and prediction of the OP performance for mobile IoV networks are investigated. A hybrid decode-amplify-forward (HDAF) relaying scheme with transmit antenna selection (TAS) is considered. The exact OP expressions are derived in a closed form, and the analytical results are verified. To realize the real-time analysis of the OP performance, an intelligent OP prediction algorithm based on the improved cuckoo search (ICS) is presented. The proposed algorithm is compared with different methods and the results show that it has a better OP prediction performance. The prediction accuracy of ICS-BP can be increased by 51.8% compared with the existing algorithms.

Investigation of Electrical Characteristic Behavior Induced by Channel-Release Process in Stacked Nanosheet Gate-All-Around MOSFETs

Abstract: In this brief, several issues attributed to the channel-release process in vertically stacked-gate-all-around MOSFETs (GAAFETs) having various nanosheet (NS) widths were rigorously investigated. Because of the finite selectivity of SiGe (sacrificial layer) etchant to Si (channel layer), Si channel is likely to be thinned during the channel-release step which is one of the key processes in stacked-GAA FET fabrication. Consequently, the thickness of channel and the interchannel space becomes variable depending on the NS width, since the etch time must be determined by the widest channel within a wafer. It results in a channel width dependence of gate work function, gate-to-drain capacitance, and channel interfacial property as well as the electrostatic gate controllability. The electrical characteristic behavior of stacked-GAAFETs induced by these effects was thoroughly investigated through process-based 3-D technology computer-aided design (TCAD) device simulation along with a transmission electron microscopy (TEM) and an energy-dispersive spectroscopy (EDS) analyses. The results confirm that width-dependent effects should be taken into account when fabricating and compact modeling the stacked-GAAFETs with various NS widths which are required for logic and static random access memory (SRAM) applications.

Design and Optimization of Triple-k Spacer Structure in Two-Stack Nanosheet FET From OFF-State Leakage Perspective

Abstract: In this article, a 5-nm node two-stack nanosheet FET with a triple-k spacer structure representing three spacer regions consisting of two inner spacers (inner spacer 1 and inner spacer 2) formed by two atomic layer deposition (ALD) processes leveraging the inner spacer formation-process method and outer spacer process of stack gate-all-around (GAA) process is proposed. Material and structure optimization was performed to confirm the effects of each spacer regions. Inner spacer 1 has a direct effect on the channel extension region. However, the inner spacer 2 is not in direct contact with the channel extension region and the gate, thus confirming the relatively indirect effect. In addition, the material dependence of the outer spacer, formed between the gate and the side region of the channel where the field is concentrated, was confirmed. By comparing the optimized triple-k spacer structure with the fully nitride spacer, the improved dynamic performance, as well as the active power and static power, was identified.