János Márkus

Bio: János Márkus is an academic researcher from Budapest University of Technology and Economics. The author has contributed to research in topics: Converters & Delta-sigma modulation. The author has an hindex of 9, co-authored 19 publications receiving 714 citations. Previous affiliations of János Márkus include Microchip Technology & Oregon State University.

Theory and applications of incremental /spl Delta//spl Sigma/ converters

Abstract: Analog-Digital (A/D) converters used in instrumentation and measurements often require high absolute accuracy, including very high linearity and negligible dc offset. The realization of high-resolution Nyquist-rate converters becomes very expensive when the resolution exceeds 16 bits. The conventional delta-sigma (/spl Delta//spl Sigma/) structures used in telecommunication and audio applications usually cannot satisfy the requirements of high absolute accuracy and very small offset. The incremental (or integrating) converter provides a solution for such measurement applications, as it has most advantages of the /spl Delta//spl Sigma/ converter, yet is capable of offset-free and accurate conversion. In this paper, theoretical and practical aspects of higher order incremental converters are discussed. The operating principles, topologies, specialized digital filter design methods, and circuit level issues are all addressed. It is shown how speed, resolution, and A/D complexity can be optimized for a given design, and how with some special digital filters improved speed/resolution ratio can be achieved. The theoretical results are verified by showing design examples and simulation results.

A low-power 22-bit incremental ADC

Abstract: This paper describes a low-power 22-bit incremental ADC, including an on-chip digital filter and a low-noise/low-drift oscillator, realized in a 0.6-mum CMOS process. It incorporates a novel offset-cancellation scheme based on fractal sequences, a novel high-accuracy gain control circuit, and a novel reduced-complexity realization for the on-chip sinc filter. The measured output noise was 0.25 ppm (2.5 muVRMS), the DC offset 2 muV, the gain error 2 ppm, and the INL 4 ppm. The chip operates with a single 2.7-5 V supply, and draws only 120 muA current during conversion

Higher-order incremental delta-sigma analog-to-digital converters

Abstract: János Márkus „Higher-order Incremental Delta-Sigma Analog-to-Digital Converters” PhD thesis Analog-to-digital conversion, which takes continuous-time, continuous amplitude signals (voltage, temperature, sound, etc.) and converts them into a series of numbers to be used for digital signal processing, is becoming the key element of the scholarly and industrial applications of measurement and data acquisition, and A/D converters are surrounding (though invisible in most cases) our everyday life. In instrumentation and measurement, there is a growing demand for A/D converters with low or medium bandwidth, but with high absolute accuracy (e.g., sensors, dcmeasurement applications). High linearity and small offset are also among the requirements, as well as small power-consumption and low sensitivity to environmental noise (such as the periodic noise coupled from the mains or digital switching noise). One solution to the problem is the incremental (or charge-balancing) ΔΣ converter, which is basically a first-order ΔΣ A/D converter, operated in transient mode. The converter represents a hybrid between the classical dual-slope converter and the ΔΣ one. This dissertation extends the operation of the incremental converter to higher-order ΔΣ loops. It discusses the basic operation of such a converter, the theoretically achievable resolution, filter design methods for the digital filter following the ΔΣ modulator, and the structure’s sensitivity to analog circuit elements imperfections. The introduced general architecture is flexible, thus it is capable to optimize the trade-off between circuit complexity and conversion accuracy. Design examples and optimization techniques are proposed to help designers selecting the best configuration for a given application. The thesis also compares the results with those found in the literature. The theoretical results are verified by simulations and also by measurements made on an integrated circuit.

IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters

Abstract: The design process will be affected in several ways. Without careful attention, the ADC interfacing could produce substandard results. Additional devices such as terminators, attenuators, and delay lines may need to be added to match signal levels and to provide signal isolation. The standard will also help incorporate evaluation considerations and test methods into the design and implementation processes.

A CMOS Temperature Sensor With a Voltage-Calibrated Inaccuracy of $\pm$ 0.15 $ ^{\circ}$ C (3 $\sigma$ ) From $-$ 55 $^{\circ}$ C to 125 $^{\circ}$ C

Abstract: This paper describes the design of a low power, energy-efficient CMOS smart temperature sensor intended for RFID temperature sensing. The BJT-based sensor employs an energy- efficient 2nd-order zoom ADC, which combines a coarse 5-bit SAR conversion with a fine 10-bit ΔΣ conversion. Moreover, a new integration scheme is proposed that halves the conversion time, while requiring no extra supply current. To meet the stringent cost constraints on RFID tags, a fast voltage calibration technique is used, which can be carried out in only 200 msec. After batch calibration and an individual room-temperature calibration, the sensor achieves an inaccuracy of ±0.15°C (3σ) from -55°C to 125°C . Over the same range, devices from a second lot achieved an inaccuracy of ±0.25°C (3σ) in both ceramic and plastic packages. The sensor occupies 0.08 mm2 in a 0.16 μm CMOS process, draws 3.4 μA from a 1.5 V to 2 V supply, and achieves a resolution of 20 mK in a conversion time of 5.3 msec. This corresponds to a minimum energy dissipation of 27 nJ per conversion.

CMOS Image Sensor With Per-Column ΣΔ ADC and Programmable Compressed Sensing

Abstract: A CMOS image sensor architecture with built-in single-shot compressed sensing is described. The image sensor employs a conventional 4-T pixel and per-column ΣΔ ADCs. The compressed sensing measurements are obtained via a column multiplexer that sequentially applies randomly selected pixel values to the input of each ΣΔ modulator. At the end of readout, each ADC outputs a quantized value of the average of the pixel values applied to its input. The image is recovered from the random linear measurements off-chip using numerical optimization algorithms. To demonstrate this architecture, a 256x256 pixel CMOS image sensor is fabricated in 0.15 μm CIS process. The sensor can operate in compressed sensing mode with compression ratio 1/4, 1/8, or 1/16 at 480, 960, or 1920 fps, respectively, or in normal capture mode with no compressed sensing at a maximum frame rate of 120 fps. Measurement results demonstrate capture in compressed sensing mode at roughly the same readout noise of 351 μVrms and power consumption of 96.2 mW of normal capture at 120 fps. This performance is achieved with only 1.8% die area overhead. Image reconstruction shows modest quality loss relative to normal capture and significantly higher image quality than downsampling.

A 2.1 M Pixels, 120 Frame/s CMOS Image Sensor With Column-Parallel $\Delta \Sigma$ ADC Architecture

Abstract: This paper presents a 2.1 M pixel, 120 frame/s CMOS image sensor with column-parallel delta-sigma (ΔΣ) ADC architecture. The use of a second-order ΔΣ ADC improves the conversion speed while reducing the random noise (RN) level as well. The ΔΣ ADC employing an inverter-based ΔΣ modulator and a compact decimation filter is accommodated within a fine pixel pitch of 2.25-μm and improves energy efficiency while providing a high frame-rate of 120 frame/s. A prototype image sensor has been fabricated with a 0.13-μm CMOS process. Measurement results show a RN of 2.4 erms- and a dynamic range of 73 dB. The power consumption of the prototype image sensor is only 180 mW. This work achieves the energy efficiency of 1.7 e-·nJ.

In Vitro Multi-Functional Microelectrode Array Featuring 59 760 Electrodes, 2048 Electrophysiology Channels, Stimulation, Impedance Measurement, and Neurotransmitter Detection Channels

Abstract: Biological cells are characterized by highly complex phenomena and processes that are, to a great extent, interdependent. To gain detailed insights, devices designed to study cellular phenomena need to enable tracking and manipulation of multiple cell parameters in parallel; they have to provide high signal quality and high-spatiotemporal resolution. To this end, we have developed a CMOS-based microelectrode array system for in vitro applications that integrates six measurement and stimulation functions, the largest number to date. Moreover, the system features the largest active electrode array area to date ( $4.48 \times 2.43$ mm2) to accommodate 59 760 electrodes, while its power consumption, noise characteristics, and spatial resolution (13.5- $\mu$ m electrode pitch) are comparable to the best state-of-the-art devices. The system includes: 2048 action potential (AP, bandwidth: 300 Hz–10 kHz) recording units, 32 local-field-potential (LFP, bandwidth: 1 Hz–300 Hz) recording units, 32 current recording units, 32 impedance measurement units, and 28 neurotransmitter detection units, in addition to the 16 dual-mode voltage-only or current/voltage-controlled stimulation units. The electrode array architecture is based on a switch matrix, which allows for connecting any measurement/stimulation unit to any electrode in the array and for performing different measurement/stimulation functions in parallel.