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Jason Miller

Bio: Jason Miller is an academic researcher from University of Cambridge. The author has contributed to research in topics: Quantum gravity & Random walk. The author has an hindex of 33, co-authored 141 publications receiving 5279 citations. Previous affiliations of Jason Miller include Stanford University & University of Geneva.


Papers
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Journal ArticleDOI
TL;DR: The Raw microprocessor research prototype uses a scalable instruction set architecture to attack the emerging wire-delay problem by providing a parallel, software interface to the gate, wire and pin resources of the chip.
Abstract: Wire delay is emerging as the natural limiter to microprocessor scalability. A new architectural approach could solve this problem, as well as deliver unprecedented performance, energy efficiency and cost effectiveness. The Raw microprocessor research prototype uses a scalable instruction set architecture to attack the emerging wire-delay problem by providing a parallel, software interface to the gate, wire and pin resources of the chip. An architecture that has direct, first-class analogs to all of these physical resources will ultimately let programmers achieve the maximum amount of performance and energy efficiency in the face of wire delay.

1,087 citations

Proceedings ArticleDOI
09 May 2012
TL;DR: DSENT, a NoC modeling tool for rapid design space exploration of electrical and opto-electrical networks, is presented and the results show the implications of different technology scenarios and the need to reduce laser and thermal tuning power in a photonic network due to their non-data-dependent nature.
Abstract: With the rise of many-core chips that require substantial bandwidth from the network on chip (NoC), integrated photonic links have been investigated as a promising alternative to traditional electrical interconnects While numerous opto-electronic NoCs have been proposed, evaluations of photonic architectures have thus-far had to use a number of simplifications, reflecting the need for a modeling tool that accurately captures the tradeoffs for the emerging technology and its impacts on the overall network In this paper, we present DSENT, a NoC modeling tool for rapid design space exploration of electrical and opto-electrical networks We explain our modeling framework and perform an energy-driven case study, focusing on electrical technology scaling, photonic parameters, and thermal tuning Our results show the implications of different technology scenarios and, in particular, the need to reduce laser and thermal tuning power in a photonic network due to their non-data-dependent nature

529 citations

Journal ArticleDOI
TL;DR: In this paper, the authors studied flow lines of the Gaussian free field and showed that they can be interpreted as the rays of a random geometry with purely imaginary curvature, and they extended the fundamental existence and uniqueness results about these paths to the case that the paths intersect the boundary.
Abstract: Fix constants $$\chi >0$$ and $$\theta \in [0,2\pi )$$ , and let h be an instance of the Gaussian free field on a planar domain. We study flow lines of the vector field $$e^{i(h/\chi +\theta )}$$ starting at a fixed boundary point of the domain. Letting $$\theta $$ vary, one obtains a family of curves that look locally like $$\hbox {SLE}_\kappa $$ processes with $$\kappa \in (0,4)$$ (where $$\chi = \tfrac{2}{\sqrt{\kappa }} -\tfrac{ \sqrt{\kappa }}{2}$$ ), which we interpret as the rays of a random geometry with purely imaginary curvature. We extend the fundamental existence and uniqueness results about these paths to the case that the paths intersect the boundary. We also show that flow lines of different angles cross each other at most once but (in contrast to what happens when h is smooth) may bounce off of each other after crossing. Flow lines of the same angle started at different points merge into each other upon intersecting, forming a tree structure. We construct so-called counterflow lines ( $$\hbox {SLE}_{16/\kappa }$$ ) within the same geometry using ordered “light cones” of points accessible by angle-restricted trajectories and develop a robust theory of flow and counterflow line interaction. The theory leads to new results about $$\hbox {SLE}$$ . For example, we prove that $$\hbox {SLE}_\kappa (\rho )$$ processes are almost surely continuous random curves, even when they intersect the boundary, and establish Duplantier duality for general $$\hbox {SLE}_{16/\kappa }(\rho )$$ processes.

281 citations

Posted Content
TL;DR: In this paper, the authors present an explicit and canonical way to embed the Liouville quantum gravity (LQG) sphere in a space-filling curve, which describes the interface between the trees.
Abstract: There is a simple way to "glue together" a coupled pair of continuum random trees (CRTs) to produce a topological sphere. The sphere comes equipped with a measure and a space-filling curve (which describes the "interface" between the trees). We present an explicit and canonical way to embed the sphere in ${\mathbf C} \cup \{ \infty \}$. In this embedding, the measure is Liouville quantum gravity (LQG) with parameter $\gamma \in (0,2)$, and the curve is space-filling SLE$_{\kappa'}$ with $\kappa' = 16/\gamma^2$. Achieving this requires us to develop an extensive suite of tools for working with LQG surfaces. We explain how to conformally weld so-called "quantum wedges" to obtain new quantum wedges of different weights. We construct finite-volume quantum disks and spheres of various types, and give a Poissonian description of the set of quantum disks cut off by a boundary-intersecting SLE$_{\kappa}(\rho)$ process with $\kappa \in (0,4)$. We also establish a Levy tree description of the set of quantum disks to the left (or right) of an SLE$_{\kappa'}$ with $\kappa' \in (4,8)$. We show that given two such trees, sampled independently, there is a.s. a canonical way to "zip them together" and recover the SLE$_{\kappa'}$. The law of the CRT pair we study was shown in an earlier paper to be the scaling limit of the discrete tree/dual-tree pair associated to an FK-decorated random planar map (RPM). Together, these results imply that FK-decorated RPM scales to CLE-decorated LQG in a certain "tree structure" topology.

221 citations

Proceedings ArticleDOI
25 Aug 2003
TL;DR: This work presents the power management facilities of the 16-tile Raw microprocessor, which selectively turns on and off 48 SRAM macros, 96 functional unit clusters, 32 fetch units, and over 250 unique processor pipeline stages, all according to the needs of the computation and environment at hand.
Abstract: Tiled architectures provide a paradigm for designers to turn silicon resources into processors with burgeoning quantities of programmable functional units and memories. The architecture has a dual responsibility: first, it must expose these resources in a way that is programmable. Second, it needs to manage the power associated with such resources. We present the power management facilities of the 16-tile Raw microprocessor. This design selectively turns on and off 48 SRAM macros, 96 functional unit clusters, 32 fetch units,and over 250 unique processor pipeline, stages, all according to the needs of the computation and environment at hand.

181 citations


Cited by
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Journal ArticleDOI
TL;DR: The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.
Abstract: The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures. This survey presents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. First, research relating to the actual network design is reviewed. Then system level design and modeling are discussed. We also evaluate performance analysis techniques. The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.

1,720 citations

Journal ArticleDOI
01 Aug 2004
TL;DR: This paper presents Brook for GPUs, a system for general-purpose computation on programmable graphics hardware that abstracts and virtualizes many aspects of graphics hardware, and presents an analysis of the effectiveness of the GPU as a compute engine compared to the CPU.
Abstract: In this paper, we present Brook for GPUs, a system for general-purpose computation on programmable graphics hardware. Brook extends C to include simple data-parallel constructs, enabling the use of the GPU as a streaming co-processor. We present a compiler and runtime system that abstracts and virtualizes many aspects of graphics hardware. In addition, we present an analysis of the effectiveness of the GPU as a compute engine compared to the CPU, to determine when the GPU can outperform the CPU for a particular algorithm. We evaluate our system with five applications, the SAXPY and SGEMV BLAS operators, image segmentation, FFT, and ray tracing. For these applications, we demonstrate that our Brook implementations perform comparably to hand-written GPU code and up to seven times faster than their CPU counterparts.

1,288 citations

Proceedings ArticleDOI
20 Apr 2009
TL;DR: The development of ORION 2.0, an extensive enhancement of the original ORION models which includes completely new subcomponent power models, area models, as well as improved and updated technology models, confirms the need for accurate early-stage NoC power estimation.
Abstract: As industry moves towards many-core chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constraint, early-stage estimation of NoC power has become crucially important. ORION [29] was amongst the first NoC power models released, and has since been fairly widely used for early-stage power estimation of NoCs. However, when validated against recent NoC prototypes -- the Intel 80-core Teraflops chip and the Intel Scalable Communications Core (SCC) chip -- we saw significant deviation that can lead to erroneous NoC design choices. This prompted our development of ORION 2.0, an extensive enhancement of the original ORION models which includes completely new subcomponent power models, area models, as well as improved and updated technology models. Validation against the two Intel chips confirms a substantial improvement in accuracy over the original ORION. A case study with these power models plugged within the COSI-OCC NoC design space exploration tool [23] confirms the need for, and value of, accurate early-stage NoC power estimation. To ensure the longevity of ORION 2.0, we will be releasing it wrapped within a semi-automated flow that automatically updates its models as new technology files become available.

799 citations

Proceedings Article
01 Jan 1972
TL;DR: In this paper, the main theoretical and experimental developments to date in Integrated Optics are reviewed, including material considerations, guiding mechanisms, modulation, coupling and mode losses, as well as the fabrication and applications of periodic thin film structures.
Abstract: In order to enable optical systems to operate with a high degree of compactness and reliability it is necessary to combine large number of optical functions in small monolithic structures. A development, somewhat reminiscent of that that took place in Integrated Electronics, is now beginning to take place in optics. The initial challenge in this emerging field, known appropriately as "Integrated Optics", is to demonstrate the possibility of performing basic optical functions such as light generation, coupling, modulation, and guiding in Integrated Optical configurations. The talk will review the main theoretical and experimental developments to date in Integrated Optics. Specific topics to be discussed include: Material considerations, guiding mechanisms, modulation, coupling and mode losses. The fabrication and applications of periodic thin film structures will be discussed.

786 citations

Journal ArticleDOI
TL;DR: This paper provides a general description of NoC architectures and applications and enumerates several related research problems organized under five main categories: Application characterization, communication paradigm, communication infrastructure, analysis, and solution evaluation.
Abstract: To alleviate the complex communication problems that arise as the number of on-chip components increases, network-on-chip (NoC) architectures have been recently proposed to replace global interconnects. In this paper, we first provide a general description of NoC architectures and applications. Then, we enumerate several related research problems organized under five main categories: Application characterization, communication paradigm, communication infrastructure, analysis, and solution evaluation. Motivation, problem description, proposed approaches, and open issues are discussed for each problem from system, microarchitecture, and circuit perspectives. Finally, we address the interactions among these research problems and put the NoC design process into perspective.

733 citations