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Jayashree Saxena

Bio: Jayashree Saxena is an academic researcher from Texas Instruments. The author has contributed to research in topics: Automatic test pattern generation & Scan chain. The author has an hindex of 11, co-authored 24 publications receiving 698 citations.

Papers
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Proceedings ArticleDOI
26 Oct 2004
TL;DR: Case study information on ATPG- and DFT-based solutions for test power reduction is presented and ICs have been observed to fail at specified minimum operating voltages during structured at-speed testing while passing all other forms of test.
Abstract: It is a well-known phenomenon that test power consumption may exceed that of functional operation. ICs have been observed to fail at specified minimum operating voltages during structured at-speed testing while passing all other forms of test. Methods exist to reduce power without dramatically increasing pattern volume for a given coverage. We present case study information on ATPG- and DFT-based solutions for test power reduction.

285 citations

Proceedings ArticleDOI
30 Oct 2001
TL;DR: A scheme for reducing power is presented and analysis results on an industrial design are provided and it is shown that circuit switching activity during scan shifting is high and results in high average and instantaneous power consumption.
Abstract: Power consumption during scan testing is becoming a concern. Circuit switching activity during scan shifting is high and results in high average and instantaneous power consumption. This paper presents a scheme for reducing power and provides analysis results on an industrial design.

183 citations

Proceedings ArticleDOI
18 Oct 1998
TL;DR: Practical experiences in applying a bridging fault based diagnosis technique to a TI ASIC design are presented for units into which known bridging defects have been introduced via a focused ion beam (FIB) machine.
Abstract: Automated fault diagnosis based on the stuck-at fault model is not always effective. This paper presents practical experiences in applying a bridging fault based diagnosis technique to a TI ASIC design. Results are presented for units into which known bridging defects have been introduced via a focused ion beam (FIB) machine.

30 citations

Proceedings ArticleDOI
03 Oct 2000
TL;DR: This paper evaluates an exhaustive set of test orderings over a variety of assumed execution parameters to analyze their effects on overall tester time consumption.
Abstract: The order in which the various test types are applied can have an impact on the overall efficiency of the test operation. Furthermore, the speed at which the tests can be executed and the latency of defect detection are also important factors. In this paper, we evaluate an exhaustive set of test orderings over a variety of assumed execution parameters to analyze their effects on overall tester time consumption.

27 citations

Patent
09 Mar 2007
TL;DR: In this paper, the authors describe a method of adapting conventional scan architectures into a low power scan architecture, which allows a larger number of circuits (such as DSP or CPU core circuits) to be tested in parallel without consuming too much power within the IC/die.
Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

26 citations


Cited by
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Proceedings ArticleDOI
01 Sep 2003
TL;DR: This paper discusses the prac- tical issues associated with power consumption during at-speed tests, and delineates in more detail the nature of power-related phenomena encountered in structured speed tests.
Abstract: At-speed test has become a requirement in IC tech- nologies below 180 nm. Unfortunately, test mode switching activity and IR-drop present special chal- lenges to the successful application of structural at- speed tests. In this paper we characterize these prob- lems on commercial ASICs in order to understand how to implement more effective solutions. consumption. Depending on such parameters as gate count, DFT strategies, package type, and other fac- tors, the impact of this problem can range from non- existent to severe. In this paper, we discuss the prac- tical issues associated with power consumption during at-speed tests. We begin by delineating in more detail the nature of power-related phenomena encountered in structured speed tests. We talk about various de- sign features that can be applied to somewhat miti- gate test mode power dissipation. In Section 2, we give a more precise definition of the IR-drop problem which is the focus of this pa- per. We compare IR-drop in slow speed and at-speed structural tests, and also compare it with functional IR-drop. We narrow the focus further to the topic of toggle activity or "switching density" during struc- tured at-speed tests. In Section 3.4 we describe the notion of "quiet" patterns and how they are gener- ated. We follow up with a report of the results we have obtained in experimentation on industrial ASIC designs. Finally we give our suggestions for future work in this area and conclude the paper.

404 citations

Proceedings ArticleDOI
L. Whetsel1
03 Oct 2000
TL;DR: A method of adapting conventional scan architectures such that they operate in a low power mode during test so that they maintain the test times of the pre-adapted scan architectures.
Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. This paper describes a method of adapting conventional scan architectures such that they operate in a low power mode during test. The adapted scan architectures maintain the test times of the pre-adapted scan architectures. Also, the adaptation occurs in a manner that enables the test patterns of the pre-adapted scan architecture to be directly reusable in the adapted scan architecture.

305 citations

Proceedings ArticleDOI
26 Oct 2004
TL;DR: Case study information on ATPG- and DFT-based solutions for test power reduction is presented and ICs have been observed to fail at specified minimum operating voltages during structured at-speed testing while passing all other forms of test.
Abstract: It is a well-known phenomenon that test power consumption may exceed that of functional operation. ICs have been observed to fail at specified minimum operating voltages during structured at-speed testing while passing all other forms of test. Methods exist to reduce power without dramatically increasing pattern volume for a given coverage. We present case study information on ATPG- and DFT-based solutions for test power reduction.

285 citations

Proceedings ArticleDOI
01 Oct 2006
TL;DR: Experimental results presented for benchmark and industrial circuits demonstrate the effectiveness of the proposed method called Preferred Fill to reduce average and peak power dissipation during capture cycles of launch off capture delay fault tests.
Abstract: When the response to a test vector is captured by state elements in scan based tests, the switching activity of the circuit may be large resulting in abnormal power dissipation and supply current demand High supply current may cause excessive supply voltage droops leading to larger gate delays which may cause good chips to fail tests This paper presents a scalable approach called Preferred Fill to reduce average and peak power dissipation during capture cycles of launch off capture delay fault tests Experimental results presented for benchmark and industrial circuits demonstrate the effectiveness of the proposed method

247 citations

Proceedings Article
01 Jan 1988
TL;DR: FXT as mentioned in this paper is a software tool which implements inductive fault analysis for CMOS circuits and extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence.
Abstract: FXT is a software tool which implements inductive fault analysis for CMOS circuits. It extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence. Five commercial CMOS circuits are analyzed using FXT. Of the extracted faults, approximately 50% can be modeled by single-line stuck-at 0/1 fault model. Faults extracted from two circuits are simulated with the switch-level fault simulator FMOSSIM. The test set provided by the circuits' manufacturer, which detects 100% of the single-line stuck-at 0/1 faults, detected between 73% and 89% of the simulated faults.<>

244 citations