Jayesh More

Bio: Jayesh More is an academic researcher from VIT University. The author has contributed to research in topics: Serial port & Asynchronous communication. The author has an hindex of 1, co-authored 1 publications receiving 2 citations.

FPGA implementation of universal asynchronous transmitter and receiver

Abstract: The proposed work in this paper describes the implementation of universal asynchronous transmitter and receiver, that is UART. The UART is a type of a serial communication protocol which serves the purpose of full duplex communication over a serial link. The UART here in is described by hardware description language that is Verilog HDL. The Verilog HDL code has been simulated in the ModelSim 10.1d and implemented on Altera DE1 board.

Design and Implementation of 1553B Bus Controller on FPGA

Abstract: MIL-STD 1553B serial bus is used in spacecraft for information exchange between subsystems. The three main elements of this 1553B bus are Bus Controller, Remote Terminal and Bus Monitor. This paper describes about the design and implementation of bus controller for a test system that focuses on the Test and Evaluation (T&E) of Onboard Bus interface (1553B) system. The design and implementation is carried out using Quartus 13.1.4 Web Edition on custom made Cyclone III FPGA board.

Multi-Master AMBA AHB Protocol Verification Using TLM Based UVM Environment

Abstract: In the due course of time, due to rising development cost and density of VLSI chips and turnaround time, it turns out to be critical to have a verification methodology, which empowers first pass chips to be entirely functional and error free. Universal Verification Methodology (UVM) facilitates the communication through TLM interface. On account of its excellent architecture of AMBA and simplicity of AHB bus it has been widely used in several SOC designs. This paper is focused on developing a Verification IP (VIP) for Multi-master AMBA AHB protocol using System Verilog based UVM environment. AMBA-AHB provides a high bandwidth system bus which can perform multiple operations in parallel. This project also depicts how Verification IP is used to verify the AHB Components-Arbiter, Slave, Master and Decoder. With the UVM based VIP, it was able to achieve MDV (Metric Driven Verification) and assertion based verification which has drastically minimized the time spent on verification of a design.The Verification IP is developed using Cadence tool Ncsim and can be reused to verify any AHB based system design.