scispace - formally typeset
Search or ask a question

Showing papers by "Jean-Michel Portal published in 2000"


Proceedings ArticleDOI
23 May 2000
TL;DR: The objective of this paper is to generate an application-oriented test procedure to be used by a FPGA user in a given application and it is demonstrated that test pattern generation can be significantly accelerated by removing most of the AC-redundant faults.
Abstract: The objective of this paper is to generate an application-oriented test procedure to be used by a FPGA user in a given application General definitions concerning the specific problem of testing RAM-based FPGAs are first given such as the important concept of 'AC-non-redundant fault' Using a set of circuits implemented on a XILINX 4000E, it is shown that a classical test pattern generation performed on the circuit netlist gives a low AC-non-redundant fault coverage and it is pointed out that test pattern generation performed on a FPGA representation is required It is then demonstrated that test pattern generation performed on the FPGA representation can be significantly accelerated by removing most of the AC-redundant faults Finally, a technique is proposed to even more accelerate the test pattern generation process by using a reduced FPGA description

20 citations


Proceedings ArticleDOI
04 Dec 2000
TL;DR: An Application-Oriented Test Procedure to be used by a FPGA user in a given application and a procedure called TOF is described to validate the proposed approach on benchmark circuits.
Abstract: The objective of this paper is to generate an Application-Oriented Test Procedure to be used by a FPGA user in a given application. General definitions concerning the specific problem of testing RAM-based FPGAs are first given such as the important concept of 'AC-non-redundant fault." Then, it is commented that a classical test pattern generation performed on the circuit netlist gives a low AC-non-redundant fault coverage and it is pointed out that test pattern generation performed on a FPGA representation is required. It is also commented that test pattern generation performed on the FPGA representation can be significantly accelerated by different techniques. A procedure called TOF is described to validate the proposed approach on benchmark circuits.

16 citations


Journal ArticleDOI
01 Oct 2000
TL;DR: This paper addresses the problem of testing the configurable modules used in the local interconnect of SRAM-based FPGAs by demonstrating that a n address bit Configurable Interface Multiplexer requires N = 2n test configurations considering a stuck-at as well as a functional fault model.
Abstract: This paper addresses the problem of testing the configurable modules used in the local interconnect of SRAM-based FPGAs. First, it is demonstrated that a n address bit Configurable Interface Multiplexer requires N e 2n test configurations considering a stuck-at as well as a functional fault model. Second, a logic cell with a set of k input Configurable Interface Modules with n address bits is analyzed and it is proven that the set of CIMs can be tested in parallel making the number of required test configurations equal to N e 2n. Third, it is shown that the complete circuit i.e. a m × m array of sets of k Configurable Interface Multiplexers with n address bits can be tested with only N e 2n test configurations using the XOR tree and shift register structures.

12 citations


Journal ArticleDOI
TL;DR: An approach to minimize the number of test configurations for testing the logic cells of a RAM-based FPGA taking into account the configurability of such flexible device is described.
Abstract: This paper describes an approach to minimize the number of test configurations for testing the logic cells of a RAM-based FPGA taking into account the configurability of such flexible device. The proposed approach concerns the XILINX 4000 family. On this example of FPGA, a bottom-up test technique is first used to generate test configurations for the elementary modules, then test configurations for a single logic cell, and finally test configurations for the m × m array of logic cells. In this bottom-up technique, it is shown that the key point is the minimization of the number of test configurations for a logic cell. An approach for the logic cell of the XILINX4000 family is then described to define a minimum number of test configurations knowing the test configurations of its logic modules. This approach gives only 5 test configurations for the XILINX4000 family while the previous published works concerning Boolean testing of this FPGA family gives 8 or 21 test configurations.

7 citations


Proceedings ArticleDOI
18 Sep 2000
TL;DR: It is pointed out that a high AC-non-redundant fault coverage can be obtained only by using an adequate FPGA representation and a procedure called TOF is described to validate the proposed approach on benchmark circuits.
Abstract: This paper studies the test pattern generation problem for FPGA implemented combinational circuits. General definitions concerning the specific problem of testing RAM-based FPGAs are first given such as the important concept of manufacturing-oriented test procedure, application-oriented test procedure and AC-non-redundant fault. Then, the test pattern generation problem is discussed and it is pointed out that a high AC-non-redundant fault coverage can be obtained only by using an adequate FPGA representation. It is also shown that test pattern generation performed on the FPGA representation can be significantly accelerated by different techniques. A procedure called TOF is described to validate the proposed approach on benchmark circuits.

4 citations