Showing papers by "Jean-Michel Portal published in 2001"

IS-FPGA : a new symmetric FPGA architecture with implicit scan

Abstract: Proposes a new and original FPGA architecture with testability facilities. It is first demonstrated that classical FPGA architectures do not allow one to efficiently implement sequential circuits with a scan chain. It is consequently proposed to modify the architecture of classical FPGAs in order to create an implicit-scan chain into the FPGA itself called implicit scan FPGA (IS-FPGA). Using this new FPGA architecture, any sequential circuit implemented into the FPGA is 'implicitly scanned'. An original and optimal implementation of the proposed architecture is given with minimum area overhead and absolutely no delay impact. Additionally the technique is transparent for the user as well as for the FPGA mapping tools. Finally, it is demonstrated that the implicit-scan concept allows 'over-scan' of sequential circuits resulting in highly testable circuits.

Analyzing bridging faults impact on EEPROM cell array

Abstract: The objective of this paper is to present a specific EEPROM functional fault model related to the impact of bridging faults in the array of cells. Moreover, the evolution of these functional faults throughout the useful life of the memory is established. In this aim, a hierarchical overview from the array structure down to the floating gate transistor simulation model is given. A set of bridging faults is defined with their corresponding stimuli. Finally, a representative simulation example is detailed.

A Discussion on Test Pattern Generation for FPGA—Implemented Circuits

Abstract: The objective of this paper is to generate a Application-Oriented Test Procedure to be used by a FPGA user in a given application. General definitions concerning the specific problem of testing RAM-based FPGAs are first given such as the important concept of ‘AC-non-redundant fault.’ Using a set of circuits implemented on a XILINX 4000E, it is shown that a classical test pattern generation performed on the circuit netlist gives a low AC-non-redundant fault coverage and it is pointed out that test pattern generation performed on a FPGA representation is required. It is then demonstrated that test pattern generation performed on the FPGA representation can be significantly accelerated by removing most of the AC-redundant faults. Finally, a technique is proposed to even more accelerate the test pattern generation process by using a reduced FPGA description.