Showing papers by "Jean-Michel Portal published in 2014"
TL;DR: In this article, a physics-based compact model used in electrical simulator for bipolar OxRAM memories is confronted to experimental electrical data and the excellent agreement with these data suggests that this model can be confidently implemented into circuit simulators for design purpose.
Abstract: Emerging nonvolatile memories based on resistive switching mechanisms pull intense research and development efforts from both academia and industry. Oxide-based resistive random access memories (OxRAM) gather noteworthy performances, such as fast WRITE/READ speed, low power, high endurance, and large integration density that outperform conventional flash memories. To fully explore new design concepts, such as distributed memory in logic or biomimetic architectures, robust OxRAM compact models must be developed and implemented into electrical simulators to assess performances at a circuit level. In this paper, we propose a physics-based compact model used in electrical simulator for bipolar OxRAM memories. After uncovering the theoretical background and the set of relevant physical parameters, this model is confronted to experimental electrical data. The excellent agreement with these data suggests that this model can be confidently implemented into circuit simulators for design purpose.
109 citations
TL;DR: A theoretical investigation of synchronous NV logic gates based on RS memories (RS-NVL) is presented and special design techniques and strategies are proposed to optimize the structure according to different resistive characteristics of NVMs.
Abstract: Emerging non-volatile memories (NVM) based on resistive switching mechanism (RS) such as STT-MRAM, OxRRAM and CBRAM etc., are under intense R&D investigation by both academics and industries. They provide high write/read speed, low power and good endurance (e.g., > 1012) beyond mainstream NVMs, which allow them to be embedded directly with logic units for computing purpose. This integration could increase significantly the power/die area efficiency, and then overcome definitively the power/speed bottlenecks of modern VLSIs. This paper presents firstly a theoretical investigation of synchronous NV logic gates based on RS memories (RS-NVL). Special design techniques and strategies are proposed to optimize the structure according to different resistive characteristics of NVMs. To validate this study, we simulated a non-volatile full-adder (NVFA) with two types of NVMs: STT-MRAM and OxRRAM by using CMOS 40 nm design kit and compact models, which includes related physics and experimental parameters. They show interesting power, speed and area gain compared with synchronized CMOS FA while keeping good reliability.
98 citations
TL;DR: This paper presents compact models of the bipolar OxRAM memory based on physical phenomenons implemented in electrical simulators for single device up to circuit level.
Abstract: Emerging non-volatile memories based on resistive switching mechanisms attract intense R&D efforts from both academia and industry. Oxide-based Resistive Random Acces Memories (OxRAM) gather noteworthy performances, such as fast write/read speed, low power and high endurance outperforming therefore conventional Flash memories. To fully explore new design concepts such as distributed memory in logic, OxRAM compact models have to be developed and implemented into electrical simulators to assess performances at a circuit level. In this paper, we present compact models of the bipolar OxRAM memory based on physical phenomenons. This model was implemented in electrical simulators for single device up to circuit level. J. Low Power Electron. Appl. 2014, 4 2
27 citations
TL;DR: An overview of NVFF architecture flavors for various emerging memory technologies is given and non-volatile flip-flops (NVFFs) seem a promising candidate to replace the retention latch.
26 citations
TL;DR: This paper proposes to integrate non-volatile resistive memories in the configuration cells and registers in order to instantly restore the FPGA context and shows that if the circuit is in the ‘ON’ state for less than 42% of time, non-Volatile FPGa starts saving energy compared to classical FPGAs.
23 citations
TL;DR: The design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells with a particular focus on reliability and power performance investigation is presented.
17 citations
24 Mar 2014
TL;DR: The first application is FPGA, one of the first architecture that can benefit the most from ReRAM integration to reduce footprint and save energy, and the second application relates to ultra-low-power systems and the way to obtain an instantaneous "freeze" mode in devices for Internet of Things.
Abstract: Recent announcement of 16Gbits Resistive memory from Sony shows the trend to quickly adopt resistive memories as an alternative to DRAM. However, using ReRAM for embedded computing is still a futuristic goal. This paper approaches two applications based on ReRAM-devices for gaining area, performance or power consumption. The first application is FPGA, one of the first architecture that can benefit the most from ReRAM integration to reduce footprint and save energy. The second application relates to ultra-low-power systems and the way to obtain an instantaneous "freeze" mode in devices for Internet of Things.
9 citations
25 Sep 2014
TL;DR: This paper describes different solutions to decrease dynamic consumption of circuits processed on an embedded non-volatile memories CMOS 80 nm technology and demonstrates up to 25 % in dynamic power reduction without degrading performances and static leakages of devices.
Abstract: This paper describes different solutions to decrease dynamic consumption of circuits processed on an embedded non-volatile memories CMOS 80 nm technology. Up to 25 % in dynamic power reduction is demonstrated without degrading performances and static leakages of devices and above all, with full DMR compliancy. Ring oscillator designs are used to estimate the dynamic power gain, comparing new development process (B) to reference process (A) currently in use in manufacturing.
8 citations
12 Mar 2014
TL;DR: A way of improvement of an oscillator concept, dedicated to detection and tracking of low energy particles with low fluxes, is presented, based on an indirect detection of the current generated at the input of the detection chain through a VCO response.
Abstract: A way of improvement of an oscillator concept, dedicated to detection and tracking of low energy particles with low fluxes, is presented. The solution is based on an indirect detection of the current generated at the input of the detection chain, through a VCO response. In order to improve the correlation between the input current and the oscillator response, a new way of VCO implementation is proposed. The new output parameter variations are analyzed.
3 citations
06 May 2014
TL;DR: A multiplexed test structure able to measure a large number of transistor threshold voltages within a scribe line and post-layout simulations are presented to validate the concept for transistor matching characterization.
Abstract: This paper presents a multiplexed test structure able to measure a large number of transistor threshold voltages within a scribe line. To achieve this, switches are used to select a single transistor among others in a small multiplexed array. A study to evaluate the influence of this multiplexing system on electrical measurement is conducted. Post-layout simulations are presented to validate the concept for transistor matching characterization.
1 citations
01 Oct 2014
TL;DR: In this paper, a non-volatile flip-flop (NVFF) was designed as an OxRAM-based pulsed latch tied to a regular FF for ultra-wide voltage range applications.
Abstract: Emerging connected devices operating on battery or harvested energy sources highlight the need for ultra-low standby power design. Including non-volatility in flip-flops (FF) allows nullifying the power consumption in sleep mode, while maintaining the system state. Most of the reported solutions require FF modifications while increasing their complexity. This paper presents a non-volatile flip-flop (NVFF) designed as an OxRAM-based pulsed latch tied to a regular FF for ultra-wide voltage range applications. In 28nm CMOS FDSOI, adding non-volatility cut-off the FF leakage at the cost of 63pJ of data store and restore energy and less than 15% of delay penalty.
07 Jul 2014
TL;DR: A new way of monitoring critical parameters directly inside circuits, able to transform a circuit into a test vehicle, is introduced: the concept is called topological exchange.
Abstract: This paper introduces a new way of monitoring critical parameters directly inside circuits. It describes a flow able to transform a circuit into a test vehicle: the concept is called topological exchange. The principle is to remap existing standard cells to create monitoring functions. The flow is detailed through a specific example of oxide thickness monitoring and the method is validated with post-layout simulations.