Jean-Michel Portal

Bio: Jean-Michel Portal is an academic researcher from Centre national de la recherche scientifique. The author has contributed to research in topics: Resistive random-access memory & Artificial neural network. The author has an hindex of 25, co-authored 136 publications receiving 2047 citations. Previous affiliations of Jean-Michel Portal include Alternatives & Aix-Marseille University.

A New Embedded NVM Thin Film Cell for Low Voltage Applications

Abstract: Low voltage Non-Volatile-Memories (NVM) are a challenge for embedded applications. Logic device platforms go slowly but surely to thin silicon film technology. Based on an advanced CMOS device, SQeRAM cell demonstrates here for the first time its potential for embedded NVM applications. It operates with a 3V supply only. Both threshold voltage and mobility variations are the basis of its 300mV and more memory windows. This ∆VT is obtained with a density of 10 trapped electrons per cm. Introduction Non-Volatile-Memories architectures are facing major technological efforts [1]. Proposals to solve scaling issues are focused on gate stack shrink keeping the highest control gate coupling factor. As a consequence in a e r future, the floating gate should be abandoned to th e profit of local trapping using nanocristals [2] or trapping layer such as nitride [3]. In addition non-volatile memories are being developed to be compatible with future thin silicon film CMOS technologies: for FinFet [4] and Silicon-On-Nothing (SON) architectures [5] [6]. SQeRAM (SON based Quasinon-volatile RAM) architecture has been proposed fo r low voltage non-volatile memory cell to address embedde d NVM needs [7]. Electrical behavior of this cell is summarized in the following after a short description of process and morphology. Process and Technology SQeRAM process is described Figure 1. A doubleepitaxy of SiGe and Si is performed on a bulk subst rate. A gate stack is realized with nitride offsets, sacrif icial oxide spacers and hard mask (A). Then gate stack and thin silicon film are protected during the junction etch (B). A partial removal of SiGe creates notches, called wings, situ ated under the gate (C). Wings are filled with thin ONO stack and N+ in situ doped Polysilicon depositions (D). Then severa l anisotropic etches prepare the surfaces for the las t epitaxy (E), Source and Drain regrow keeping the wings safe (F). Figure 2 is a TEM cross-section of a resulted devic e which has been electrically characterized. As one can conclude, memory charges are stored under the channel. The original gate stack of the l ogic devices is conserved. A Thin ONO is introduced for low volt age biases. The thickness and quality of this dielectri c layer determines retention of the device. PolySilicon win gs allow to apply biases under channel without any additiona l contact. Memory principle: electrical properties SQeRAM operates a less than 3V supply. The biases used in this paper are summarized in Table 1. Read operation has been performed here with drain voltage of 0.1V. Figure 3 shows after a Write sweep a 300mV memory window wit h a maximum bias of 2.5V on the drain. Forward (FD) and Reversed (RD) Diode pulses are used to vary the sto red charge. Diode bias cycling has been used to investi gate the memory ability of the devices. Figure 4 shows the typical FD/RD cycling for the 80nm long device shown Figure 2. The ∆VT observed under threshold voltage on Figure 4a) is due to stored ch arge. A mobility variation is observed Figure 4b) for inver sion regime as already observed with traps in gate oxide by [8]. Initial mobility is not completely restored by FD p ulse. The sub-threshold slope is slightly degradated after th first RD pulse Figure 4a). As the sub-threshold slope stays quite similar during the cycle, there is no more interfac e degradation after the first pulse. States 0 and 1 are respectively defined after FD an d RD pulses. Figure 5 and 6 give memory windows after FD/RD cycle for both 30Å and 50Å gate oxide devices . In Figure 7, ∆VT memory window corresponds to the difference of gate bias applied for a same curr ent in the device at both states. Memory window is higher for thick gate oxide under threshold due to a better charge effect as gate coupling is lower. Memory window in inversion regim e is better for a 30Å oxide thickness related to mobilit y variation. Memory window study TCAD simulation is used to evaluate charge density and mobility variations for 30Å gate oxide device. Figure 8 details the simulated device. Table 2 summarizes th used parameters according TEM cross-section analysis (Fi gure 2). A constant surface charge density is assumed in the ONO in both wings. Mobility and charge density have been a dapted to fit the curve (Figure 9). Simulation considers m emory effect due to a 10 13 e/cm charge density. There is a 9.5 cm.V.s mobility variation between states 0 and 1. A 20 cm.V.s mobility degradation is observed between initial curve and state 0. Figure 10 shows the resulting memory windows from simulation versus measurements. The behavior i n inversion regime (A) is reproduced: mobility variat ion is a good way to explain ∆VT increase in this regime. In far subthreshold (B) regime it is also reproduced. The sma ll difference of sub-threshold slope between the 2 sta te (Figure 6) explains ∆VT increase during the transition (C). Conclusion More than 300mV memory window can be obtained for a density of 10 13 electrons per cm. Degradation occurs in the early steps of writing. Our study has demonstra ted that SQeRAM cell memory window depends on both threshold voltage and mobility variations. Reliability enhanc ement needs more efforts on device integration and ONO st ack. Acknowledgment: This work is supported in the frame of MINAmI Europ ean project (WP6) www.fp6-minami.org Reference [1] M. Noguchi et al., \"A High-performance Multi-l evel NAND Flash Memory with 43nm-node Floating-gate Technology\", In ter ational Electron Devices Meeting (2007) pp 445 – 448 [2] G. Molas et al., \"Thorough investigation of Sinanocrystal memories with high-k interpoly dielectrics for sub-45nm node Flas h NAND applications\", International Electron Devices Meeting (2007) pp 45 3– 456 Extended Abstracts of the 2008 International Conference on Solid State Devices and Materials, Tsukuba, 2008, -830J-6-3 pp. 830-831

Programmable-resistance non-volatile memory

Abstract: A non-volatile memory including a plurality of elementary cells, each cell including: a first programmable-resistance storage element connected between first and second nodes of the cell; a first access transistor coupling the second node to a third node of the cell; and a second access transistor coupling the second node to a fourth node of the cell.

OxRAM-based pulsed latch for non-volatile flip-flop in 28nm FDSOI

Abstract: Emerging connected devices operating on battery or harvested energy sources highlight the need for ultra-low standby power design. Including non-volatility in flip-flops (FF) allows nullifying the power consumption in sleep mode, while maintaining the system state. Most of the reported solutions require FF modifications while increasing their complexity. This paper presents a non-volatile flip-flop (NVFF) designed as an OxRAM-based pulsed latch tied to a regular FF for ultra-wide voltage range applications. In 28nm CMOS FDSOI, adding non-volatility cut-off the FF leakage at the cost of 63pJ of data store and restore energy and less than 15% of delay penalty.

PCM compact model: Optimized methodology for model card extraction

Abstract: To achieve high yield on product embedding PCM memory, it is mandatory to provide to designers accurately calibrated PCM compact model. To achieve this goal, it is mandatory to develop standardized model card extraction methodology. In this paper, we present a PCM model card extraction flow based on a minimal set of static and dynamic measurements. Based on this measurement, characteristics are first obtained and model card parameters extracted without any loop back, i.e. each parameter is extracted only once on a given characteristic. After this extraction procedure, model card values are validated through a comparison with an extra characteristics SET-Low characteristic not used for the extraction.

In-Memory Resistive RAM Implementation of Binarized Neural Networks for Medical Applications

Abstract: The advent of deep learning has considerably accelerated machine learning development The deployment of deep neural networks at the edge is however limited by their high memory and energy consumption requirements With new memory technology available, emerging Binarized Neural Networks (BNNs) are promising to reduce the energy impact of the forthcoming machine learning hardware generation, enabling machine learning on the edge devices and avoiding data transfer over the network In this work, after presenting our implementation employing a hybrid CMOS - hafnium oxide resistive memory technology, we suggest strategies to apply BNNs to biomedical signals such as electrocardiography and electroencephalography, keeping accuracy level and reducing memory requirements We investigate the memory-accuracy trade-off when binarizing whole network and binarizing solely the classifier part We also discuss how these results translate to the edge-oriented Mobilenet~V1 neural network on the Imagenet task The final goal of this research is to enable smart autonomous healthcare devices

Emerging memories: resistive switching mechanisms and current status.

Abstract: The resistance switching behaviour of several materials has recently attracted considerable attention for its application in non-volatile memory (NVM) devices, popularly described as resistive random access memories (RRAMs). RRAM is a type of NVM that uses a material(s) that changes the resistance when a voltage is applied. Resistive switching phenomena have been observed in many oxides: (i) binary transition metal oxides (TMOs), e.g. TiO(2), Cr(2)O(3), FeO(x) and NiO; (ii) perovskite-type complex TMOs that are variously functional, paraelectric, ferroelectric, multiferroic and magnetic, e.g. (Ba,Sr)TiO(3), Pb(Zr(x) Ti(1-x))O(3), BiFeO(3) and Pr(x)Ca(1-x)MnO(3); (iii) large band gap high-k dielectrics, e.g. Al(2)O(3) and Gd(2)O(3); (iv) graphene oxides. In the non-oxide category, higher chalcogenides are front runners, e.g. In(2)Se(3) and In(2)Te(3). Hence, the number of materials showing this technologically interesting behaviour for information storage is enormous. Resistive switching in these materials can form the basis for the next generation of NVM, i.e. RRAM, when current semiconductor memory technology reaches its limit in terms of density. RRAMs may be the high-density and low-cost NVMs of the future. A review on this topic is of importance to focus concentration on the most promising materials to accelerate application into the semiconductor industry. This review is a small effort to realize the ambitious goal of RRAMs. Its basic focus is on resistive switching in various materials with particular emphasis on binary TMOs. It also addresses the current understanding of resistive switching behaviour. Moreover, a brief comparison between RRAMs and memristors is included. The review ends with the current status of RRAMs in terms of stability, scalability and switching speed, which are three important aspects of integration onto semiconductors.

Neuromorphic computing using non-volatile memory

Abstract: Dense crossbar arrays of non-volatile memory (NVM) devices represent one possible path for implementing massively-parallel and highly energy-efficient neuromorphic computing systems. We first revie...

Monitoring of environmental exposure to polycyclic aromatic hydrocarbons: a review

Abstract: Polycyclic aromatic hydrocarbons (PAHs) are a large group of organic compounds with two or more fused aromatic rings. They have a relatively low solubility in water, but are highly lipophilic. Most of the PAHs with low vapour pressure in the air are adsorbed on particles. When dissolved in water or adsorbed on particulate matter, PAHs can undergo photodecomposition when exposed to ultraviolet light from solar radiation. In the atmosphere, PAHs can react with pollutants such as ozone, nitrogen oxides and sulfur dioxide, yielding diones, nitro- and dinitro-PAHs, and sulfonic acids, respectively. PAHs may also be degraded by some microorganisms in the soil. PAHs are widespread environmental contaminants resulting from incomplete combustion of organic materials. The occurrence is largely a result of anthropogenic emissions such as fossil fuel-burning, motor vehicle, waste incinerator, oil refining, coke and asphalt production, and aluminum production, etc. PAHs have received increased attention in recent years in air pollution studies because some of these compounds are highly carcinogenic or mutagenic. Eight PAHs (Car-PAHs) typically considered as possible carcinogens are: benzo(a)anthracene, chrysene, benzo(b)fluoranthene, benzo(k)fluoranthene, benzo(a)pyrene (B(a)P), dibenzo(a,h)anthracene, indeno(1,2,3-cd)pyrene and benzo(g,h,i)perylene. In particular, benzo(a)pyrene has been identified as being highly carcinogenic. The US Environmental Protection Agency (EPA) has promulgated 16 unsubstituted PAHs (EPA-PAH) as priority pollutants. Thus, exposure assessments of PAHs in the developing world are important. The scope of this review will be to give an overview of PAH concentrations in various environmental samples and to discuss the advantages and limitations of applying these parameters in the assessment of environmental risks in ecosystems and human health. As it well known, there is an increasing trend to use the behavior of pollutants (i.e. bioaccumulation) as well as pollution-induced biological and biochemical effects on human organisms to evaluate or predict the impact of chemicals on ecosystems. Emphasis in this review will, therefore, be placed on the use of bioaccumulation and biomarker responses in air, soil, water and food, as monitoring tools for the assessment of the risks and hazards of PAH concentrations for the ecosystem, as well as on its limitations.