Showing papers by "Jeffrey Dean published in 1998"
Patent•
25 Nov 1998
TL;DR: In this paper, a method for estimating statistics of properties of interactions among instructions processed in a pipeline of a computer system, the pipeline having a plurality of processing stages, is presented, where a set of instructions are randomly selected from the fetched instructions, a subset of the set of selected instructions concurrently executing with each other.
Abstract: Provided is a method for estimating statistics of properties of interactions among instructions processed in a pipeline of a computer system, the pipeline having a plurality of processing stages Instructions are fetched Into a first stage of the pipeline A set of instructions are randomly selected from the fetched instructions, a subset of the set of selected instructions concurrently executing with each other A distances between the set of selected instructions is specified, and state information of the computer system is recorded while the set of selected instructions is being processed by the pipeline The recorded state information is communicated to software where it is statistically analyzed for a plurality of sets of selected instructions to estimate statistics of the interactions among sets of selected instructions
136 citations
Patent•
25 Nov 1998
TL;DR: In this paper, an apparatus is provided for sampling instructions in a processor pipeline of a system, where instructions are identified and state information of the system is sampled while a particular selected instruction is in any stage of the pipeline.
Abstract: An apparatus is provided for sampling instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus includes a fetch unit for fetching instructions into a first stage of the pipeline. Certain randomly selected instructions are identified, and state information of the system is sampled while a particular selected instruction is in any stage of the pipeline. Software is informed when the particular selected instruction leaves the pipeline so that the software can read any of the sampled state information.
107 citations
Patent•
10 Aug 1998
TL;DR: In this article, a method is described for identifying pages that are near duplicates in a linked database, where two pages are selected, a first page and a second page, and the number of outgoing links for each selected page is determined.
Abstract: A method is described for identifying pages that are near duplicates in a linked database. In the linked database, pages can have incoming links and outgoing links. Two pages are selected, a first page and a second page. For each selected page, the number of outgoing links is determined. The two pages are marked as near duplicates based on the number of common outgoing links for the two pages.
95 citations
Patent•
25 Nov 1998TL;DR: In this paper, a method for sampling the performance of a computer system is provided, which selects transactions to be processed by a particular functional unit of the computer system, while state information is stored while the selected transactions are processed by the functional unit.
Abstract: A method for sampling the performance of a computer system is provided. The computer system includes a plurality of functional units. The method selects transactions to be processed by a particular functional unit of the computer system. State information is stored while the selected transactions are processed by the functional unit. The state information is analyzed to guide optimization.
79 citations
Patent•
25 Nov 1998
TL;DR: In this paper, an apparatus is provided for sampling values of operands of instructions in a processor pipeline of a system, the pipeline having a plurality of processing stages, and instructions are fetched into a first stage of the pipeline.
Abstract: An apparatus is provided for sampling values of operands of instructions in a processor pipeline of a system, the pipeline having a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. Any one of the fetched instructions are identified as a particular selected instruction. Values of results computed during the processing of the particular selected instruction are recorded in a sampling record along with state information identifying the particular selected instruction. Software is informed whenever the particular selected instruction leaves the pipeline to read the recorded values and state information.
61 citations
Patent•
07 Dec 1998
TL;DR: In this paper, a method and apparatus for preventing topic drift in queries in hyperlinked environments uses equivalence components for ranking pages containing information that is relevant to the topic of a user query input to a search engine.
Abstract: A method and apparatus for preventing topic drift in queries in hyperlinked environments uses equivalence components for ranking pages containing information that is relevant to the topic of a user query input to a search engine. The method includes the step of providing a query to a search engine, where the query represents a predetermined topic; retrieving at least one page associated with the query; constructing a graph representing the pages in memory; creating at least one equivalence component representing a subset of the graph; processing each equivalence component; eliminating the equivalence component in accordance with whether it matches the predetermined topic; and ranking the remaining pages.
48 citations
Patent•
25 Nov 1998TL;DR: In this paper, an apparatus for sampling states of a computer system having a hierarchical memory arranged at a plurality of levels, the hierarchical memory storing data at addresses, is presented, which includes a selector for selecting memory transactions based on first state and transaction information.
Abstract: An apparatus for sampling states of a computer system having a hierarchical memory arranged at a plurality of levels, the hierarchical memory storing data at addresses. The apparatus includes a selector for selecting memory transactions based on first state and transaction information. The memory transactions are to be processed by the hierarchical memory. A trigger activates the selector based on second state and transaction information. A sampler stores states of the computer system that are identified with the selected instructions while processing the selected memory transactions in the hierarchical memory.
45 citations
Patent•
25 Nov 1998
TL;DR: In this paper, a method for analyzing memory transactions processed by memories of a computer system is proposed, where state information from a plurality of consecutive predetermined memory transactions to the selected addresses are recorded while the selected transactions are processed by the memories.
Abstract: A method analyses memory transaction processed by memories of a computer system. The method selects a set of addresses of the memories. State information from a plurality of consecutive predetermined memory transactions to the selected addresses are recorded while the selected transactions are processed by the memories. The selecting and the recording steps are repeated until a termination condition is reached. Then, the recorded state information is statistically analysed to estimate statistics of properties of the memory interactions among contexts in the computer system.
42 citations
01 Jan 1998
TL;DR: This work has designed a framework that improves on previous work by making it easy to perform graph transformations as part of iterative analysis, to run multiple analyses “in parallel” to achieve the precision of a single monolithic analysis while preserving modularity and reusability of the component analyses.
Abstract: Because dataflow analyses are difficult to implement from scratch, reusable dataflow analysis frameworks have been developed which provide generic support facilities for managing propagation of dataflow information and iteration in loops. We have designed a framework that improves on previous work by making it easy to perform graph transformations as part of iterative analysis, to run multiple analyses “in parallel” to achieve the precision of a single monolithic analysis while preserving modularity and reusability of the component analyses, and to construct contextsensitive interprocedural analyses from intraprocedural versions. We have implemented this framework in the Vortex optimizing compiler and used the framework to help build both traditional optimizations and non-traditional optimizations of dynamically-dispatched messages and first-class, lexically-nested functions.
28 citations
Patent•
25 Nov 1998
TL;DR: In this paper, a method was proposed to estimate statistics of properties of transactions processed by a memory sub-system of a computer system, where states of the system are recorded as samples while the selected transaction are processed by the memory sub system.
Abstract: A method estimates statistics of properties of transactions processed by a memory sub-system of a computer system. The method randomly selects memory transactions processed by the memory sub-system. States of the system are recorded as samples while the selected transaction are processed by the memory sub-system. The recorded states from a subset of the selected transactions are statistically analyzed to estimate statistics ofthe memory transactions.
28 citations
Patent•
25 Nov 1998
TL;DR: In this paper, a method for sampling the performance of a computer system is provided, which selects transactions to be processed by a particular functional unit of the computer system, and state information is analyzed to guide optimization.
Abstract: of EP0919919A method for sampling the performance of a computer system is provided. The computer system includes a plurality of functional units. The method selects transactions to be processed by a particular functional unit of the computer system. State information is stored while the selected transactions are processed by the functional unit. The state information is analyzed to guide optimization.
01 Jan 1998
Patent•
26 Nov 1998
TL;DR: In this article, the authors propose a device for sampling many potentially simultaneous instruction in a processor pipeline, which identifies the plural instructions to be selected when the instructions are fetched to the pipeline 111.
Abstract: PROBLEM TO BE SOLVED: To provide a device for sampling many potentially simultaneous instruction in a processor pipeline. SOLUTION: This device is the one which samples many simultaneous execution instructions in a processor pipeline of a system 100 and a pipeline 111 has plural processing steps. This device identifies the plural instructions to be selected when the instructions are fetched to the pipeline 111. Plural selected subsets of the instructions are simultaneously executed in the pipeline 111. While any of the plural selected instructions is at any step of the pipeline 111, the state information of the system is sampled. When all the selected instructions go out of the pipeline, software is notified of it and therefore, the software can read any state information.
Patent•
26 Nov 1998
TL;DR: In this article, the state of a computer system is sampled using a selector to select a memory transaction based on a first state and transaction information, followed by a trigger to operate the selector based on second state and transactions information.
Abstract: PROBLEM TO BE SOLVED: To provide a device which samples transactions used for access to data stored in the memory of a computer system. SOLUTION: This device samples the state of a computer system 100 which is constituted on plural levels and has a hierarchy memory where data are stored in addresses. This device includes a selector to select a memory transaction based on a first state and transaction information. The memory transaction should be processed by the hierarchy memory. A trigger operates the selector based on a second state and transaction information. A sampler stores the state of the computer system 100 discriminated by a selected instruction while the selected memory transaction is processed in the hierarchy memory. COPYRIGHT: (C)1999,JPO
Patent•
26 Nov 1998
TL;DR: In this article, the problem of simultaneously sampling multiple functional units by storing state information while a selected transaction is processed by the functional unit and analyzing state information so that optimization is introduced is solved.
Abstract: PROBLEM TO BE SOLVED: To simultaneously sample multiple different functional units by storing state information while a selected transaction is processed by the functional unit and analyzing state information so that optimization is introduced. SOLUTION: A marker 230 decides which transaction is marked as a selected transaction(T') 103. A trigger 210 receives a transaction 101, an event 104 and a state 130 based on a specified sampled functional unit. The corresponding functional unit processing the marked transaction 103 after the prescribed transaction is selected for sampling checks sample bits for respective processing stages and collects state information which can be used for checking. Collected state information is stored in more than one buffers. Collected information is used for introducing optimization. COPYRIGHT: (C)1999,JPO
Patent•
25 Nov 1998
Patent•
25 Nov 1998
TL;DR: In this article, an apparatus is provided for sampling multiple concurrently executing instructions in a processor pipeline of a system, where state information of the system is sampled while any of the selected instructions are in any stage of the pipeline.
Abstract: An apparatus is provided for sampling multiple concurrently executing
instructions in a processor pipeline of a system. The pipeline has a plurality
of processing stages. When the instructions are fetched into a first
stage of the pipeline, the apparatus identifies multiple selected
instructions as a subset of the instructions that one executed
concurrently in the pipeline. State
information of the system is sampled while any of the multiple selected
instructions are in any stage of the pipeline. Software is informed whenever
all of the selected instructions leave the pipeline so that the software can
read any of the state information.
Patent•
25 Nov 1998
Patent•
25 Nov 1998
TL;DR: In this article, an apparatus is provided for sampling multiple concurrently executing instructions in a processor pipeline of a system, where the instructions are fetched into a first stage of the pipeline, the apparatus identifies multiple selected instructions as a subset of the instructions that one executed concurrently in the pipeline.
Abstract: An apparatus is provided for sampling multiple concurrently executing instructions in a processor pipeline of a system The pipeline has a plurality of processing stages When the instructions are fetched into a first stage of the pipeline, the apparatus identifies multiple selected instructions as a subset of the instructions that one executed concurrently in the pipeline State information of the system is sampled while any of the multiple selected instructions are in any stage of the pipeline Software is informed whenever all of the selected instructions leave the pipeline so that the software can read any of the state information