Communication at millimeter wave (mmWave) frequencies is defining a new era of wireless communication. The mmWave band offers higher bandwidth communication channels versus those presently used in commercial wireless systems. The applications of mmWave are immense: wireless local and personal area networks in the unlicensed band, 5G cellular systems, not to mention vehicular area networks, ad hoc networks, and wearables. Signal processing is critical for enabling the next generation of mmWave communication. Due to the use of large antenna arrays at the transmitter and receiver, combined with radio frequency and mixed signal power constraints, new multiple-input multiple-output (MIMO) communication signal processing techniques are needed. Because of the wide bandwidths, low complexity transceiver algorithms become important. There are opportunities to exploit techniques like compressed sensing for channel estimation and beamforming. This article provides an overview of signal processing challenges in mmWave wireless systems, with an emphasis on those faced by using MIMO communication at higher carrier frequencies.

An Overview of Signal Processing Techniques for Millimeter Wave MIMO Systems

This tutorial presents an overview of the technological advances in millimeter-wave (mm-wave) circuit components, antennas, and propagation that will soon allow 60-GHz transceivers to provide multigigabit per second (multi-Gb/s) wireless communication data transfers in the consumer marketplace. Our goal is to help engineers understand the convergence of communications, circuits, and antennas, as the emerging world of subterahertz and terahertz wireless communications will require understanding at the intersections of these areas. This paper covers trends and recent accomplishments in a wide range of circuits and systems topics that must be understood to create massively broadband wireless communication systems of the future. In this paper, we present some evolving applications of massively broadband wireless communications, and use tables and graphs to show research progress from the literature on various radio system components, including on-chip and in-package antennas, radio-frequency (RF) power amplifiers (PAs), low-noise amplifiers (LNAs), voltage-controlled oscillators (VCOs), mixers, and analog-to-digital converters (ADCs). We focus primarily on silicon-based technologies, as these provide the best means of implementing very low-cost, highly integrated 60-GHz mm-wave circuits. In addition, the paper illuminates characterization techniques that are required to competently design and fabricate mm-wave devices in silicon, and illustrates effects of the 60-GHz RF propagation channel for both in-building and outdoor use. The paper concludes with an overview of the standardization and commercialization efforts for 60-GHz multi-Gb/s devices, and presents a novel way to compare the data rate versus power efficiency for future broadband devices.

http://faculty.poly.edu/~tsr/wp-content/uploads/publications/abstract17.pdf

State of the Art in 60-GHz Integrated Circuits and Systems for Wireless Communications

Hybrid analog/digital multiple-input multiple-output architectures were recently proposed as an alternative for fully digital-precoding in millimeter wave wireless communication systems. This is motivated by the possible reduction in the number of RF chains and analog-to-digital converters. In these architectures, the analog processing network is usually based on variable phase shifters. In this paper, we propose hybrid architectures based on switching networks to reduce the complexity and the power consumption of the structures based on phase shifters. We define a power consumption model and use it to evaluate the energy efficiency of both structures. To estimate the complete MIMO channel, we propose an open-loop compressive channel estimation technique that is independent of the hardware used in the analog processing stage. We analyze the performance of the new estimation algorithm for hybrid architectures based on phase shifters and switches. Using the estimate, we develop two algorithms for the design of the hybrid combiner based on switches and analyze the achieved spectral efficiency. Finally, we study the tradeoffs between power consumption, hardware complexity, and spectral efficiency for hybrid architectures based on phase shifting networks and switching networks. Numerical results show that architectures based on switches obtain equal or better channel estimation performance to that obtained using phase shifters, while reducing hardware complexity and power consumption. For equal power consumption, all the hybrid architectures provide similar spectral efficiencies.

Hybrid MIMO Architectures for Millimeter Wave Communications: Phase Shifters or Switches?

Hybrid analog/digital MIMO architectures were recently proposed as an alternative for fully-digitalprecoding in millimeter wave (mmWave) wireless communication systems. This is motivated by the possible reduction in the number of RF chains and analog-to-digital converters. In these architectures, the analog processing network is usually based on variable phase shifters. In this paper, we propose hybrid architectures based on switching networks to reduce the complexity and the power consumption of the structures based on phase shifters. We define a power consumption model and use it to evaluate the energy efficiency of both structures. To estimate the complete MIMO channel, we propose an open loop compressive channel estimation technique which is independent of the hardware used in the analog processing stage. We analyze the performance of the new estimation algorithm for hybrid architectures based on phase shifters and switches. Using the estimated, we develop two algorithms for the design of the hybrid combiner based on switches and analyze the achieved spectral efficiency. Finally, we study the trade-offs between power consumption, hardware complexity, and spectral efficiency for hybrid architectures based on phase shifting networks and switching networks. Numerical results show that architectures based on switches obtain equal or better channel estimation performance to that obtained using phase shifters, while reducing hardware complexity and power consumption. For equal power consumption, all the hybrid architectures provide similar spectral efficiencies.

Reactive matching is extended to wide bandwidths using the impedance property of LC-ladder filters. In this paper, we present a systematic method to design wideband low-noise amplifiers. An SiGe amplifier with on-chip matching network spanning 3-10 GHz delivers 21-dB peak gain, 2.5-dB noise figure, and -1-dBm input IP3 at 5 GHz, with a 10-mA bias current.

A 3-10-Ghz low-noise amplifier with wideband LC-ladder matching network

A 57-64-GHz low phase-error 5-bit switch-type phase shifter integrated with a low phase-variation variable gain amplifier (VGA) is implemented through TSMC 90-nm CMOS low-power technology. Using the phase compensation technique, the proposed VGA can provide appropriate gain tuning with almost constant phase characteristics, thus greatly reducing the phase-tuning complexity in a phased-array system. The measured root mean square (rms) phase error of the 5-bit phase shifter is 2° at 62 GHz. The phase shifter has a low group-delay deviation (phase distortion) of +/- 8.5 ps and an excellent insertion loss flatness of ±0.8 dB for a specific phase-shifting state, across 57-64 GHz. For all 32 states, the insertion loss is 14.6 ± 3 dB, including pad loss at 60 GHz. For the integrated phase shifter and VGA, the VGA can provide 6.2-dB gain tuning range, which is wide enough to cover the loss variation of the phase shifter, with only 1.86° phase variation. The measured rms phase error of the 5-bit phase shifter and VGA is 3.8° at 63 GHz. The insertion loss of all 32 states is 5.4 dB, including pad loss at 60 GHz, and the loss flatness is ±0.8 dB over 57-64 GHz. To the best of our knowledge, the 5-bit phase shifter presents the best rms phase error at center frequency among the V-band switch-type phase shifter.

60-GHz 5-bit Phase Shifter With Integrated VGA Phase-Error Compensation

Sub-harmonic modulator and demodulator are presented in this paper using 0.13-mum standard CMOS technology for millimeter-wave (MMW) wireless gigabit direct-conversion systems. To overcome the main problem of local oscillator (LO) leakage in direct-conversion systems, the sub-harmonically pumped scheme is selected in this mixer design. An embedded four-way quadrature divider is utilized in the sub-harmonic Gilbert-cell design to generate quadrature-phases LO signals at MMW frequency. For broadband applications, a broadband matching design formula is provided in this paper to extend the operational frequency range from 35 to 65 GHz. To improve the flatness of conversion loss at high frequency, high-impedance compensation lines are incorporated between the transconductance stage and LO switching quad of the Gilbert-cell mixer to compensate the parasitic capacitance. The sub-harmonic modulator and demodulator exhibit 6 plusmn1.5 dB and 7.5 plusmn1.5 dB measured conversion loss, respectively, from 35 to 65 GHz. For MMW wireless gigabit applications, the gigabit modulation signal test is successfully performed through the direct-conversion system in this paper. To our knowledge, this is the first demonstration of the MMW CMOS sub-harmonic modulator and demodulator that feature broadband and gigabit applications.

35–65-GHz CMOS Broadband Modulator and Demodulator With Sub-Harmonic Pumping for MMW Wireless Gigabit Applications

A compact and broadband 25-75-GHz fully integrated double-balance Gilbert-cell mixer using 90-nm standard mixed-signal/radio frequency (RF) CMOS technology is presented in this letter. A broadband matching network, LC ladder, for Gilbert-cell mixer transconductance stage design is introduced to achieve the flatness of conversion gain and good RF port impedance match over broad bandwidth. This Gilbert-cell mixer exhibits 3plusmn2dB measured conversion gain (to 50-Omega load) from 25 to 75GHz with a compact chip size of 0.30mm2. The OP1 dB of the mixer is 1dBm and -4dBm at 40 and 60GHz, respectively. To the best of our knowledge, this monolithic microwave integrated circuit is the highest frequency CMOS Gilbert-cell mixer to date

A 25–75 GHz Broadband Gilbert-Cell Mixer Using 90-nm CMOS Technology

A 55-71-GHz fully integrated power amplifier (PA) using a distributed active transformer (DAT) is implemented in 90-nm RF/MS CMOS technology. The DAT combiner, featuring efficient power combination and direct impedance transformation, is suitable for millimeter-wave (MMW) PA design. Systematic design procedures including an impedance allocation plan, a compensation line, and a gain boosting technique are presented for the MMW DAT PA. The monolithic microwave integrated circuit (MMIC) performs a high and flat small-signal gain of 26 plusmn1.5 dB from 55 to 71 GHz, which covers a full band for 60-GHz wireless personal area network applications. Using cascode devices and a DAT four-way power combination, the CMOS PA delivers 14.5- and 18-dBm saturated output power with 10.2% and 12.2% power-added efficiency under 1.8- and 3-V supply voltage, respectively, at 60 GHz. The maximum linear output power (P1 dB) is 14.5 dBm. To the best of our knowledge, the MMIC is the first demonstration of a V-band CMOS PA using a DAT combining scheme with highest linear output power among the reported 60-GHz CMOS PAs to date.

Design and Analysis of a 55–71-GHz Compact and Broadband Distributed Active Transformer Power Amplifier in 90-nm CMOS Process

In this paper, a pair of broadband, low-LO-power, low-dc-power, and high-speed up/down-conversion ring mixers are presented for multistandard millimeter-wave (MMW) radio applications. By employing a weak inversion biasing technique, the ring mixer can operate at a low LO drive level and low dc power while maintaining reasonable conversion gain performance. In addition, an IF transimpedance amplifier (TIA) buffer and wideband RF design are introduced to increase the operation speed of the mixer for MMW wireless Gigabit transmission. Using a 90-nm CMOS low-power process, the up-/down-conversion ring mixers are designed and fabricated based on the presented topology. The down-conversion ring mixer and up-conversion ring mixer exhibit flat measured conversion gain of -1 ± 2 dB and 0 ± 2 dB and dB from 40 to 110 GHz and 40 to 108 GHz, respectively. After biasing the transistors of the ring mixer core at weak inversion region, the presented down-conversion and up-conversion ring mixers can operate at low LO drive power, -2 and 0 dBm, respectively, even up to 100 GHz. For MMW wireless gigabit communication, gigabit binary phase-shift keying modulation signal test is successfully performed through a direct-conversion system in this work. The presented ring mixers are suitable for 60-GHz wireless personal area network, -E-band (71-76 GHz, 81-86 GHz, and 92-95 GHz) wireless fiber, and 77-GHz anti-collision radar applications.

Jeng-Han Tsai

Papers

60-GHz 5-bit Phase Shifter With Integrated VGA Phase-Error Compensation

35–65-GHz CMOS Broadband Modulator and Demodulator With Sub-Harmonic Pumping for MMW Wireless Gigabit Applications

A 25–75 GHz Broadband Gilbert-Cell Mixer Using 90-nm CMOS Technology

Design and Analysis of a 55–71-GHz Compact and Broadband Distributed Active Transformer Power Amplifier in 90-nm CMOS Process

Design of 40–108-GHz Low-Power and High-Speed CMOS Up-/Down-Conversion Ring Mixers for Multistandard MMW Radio Applications