Jenn-Gwo Hwu

Bio: Jenn-Gwo Hwu is an academic researcher from National Taiwan University. The author has contributed to research in topics: Oxide & Gate oxide. The author has an hindex of 18, co-authored 227 publications receiving 1386 citations. Previous affiliations of Jenn-Gwo Hwu include TSMC & National United University.

Enhancement of silicon oxidation rate due to tensile mechanical stress

Abstract: Oxidation of silicon wafers under external mechanical stress was studied in this work From the oxide thickness profile measured by an automatic ellipsometer, it was found that the oxidation kinetics of silicon was affected by the mechanical stress The tensile stress strongly enhances the oxidation rate of silicon A concept was proposed to explain this phenomenon by using a well-known physical Si–SiO2 lattice model The tensile stress in the silicon will enlarge the atom spacing of silicon and make the oxidation to be easier and faster A simulated deformation of silicon substrate under tensile stress was also given to support this concept This work is a direct evidence of the effect of mechanical stress on silicon oxidation

Electrical characterization and process control of cost-effective high-k aluminum oxide gate dielectrics prepared by anodization followed by furnace annealing

Abstract: A cost-effective technique was introduced to prepare ultrathin aluminum oxide (Al/sub 2/O/sub 3/) gate dielectrics with equivalent oxide thickness (EOT) down to 14 /spl Aring/. Al/sub 2/O/sub 3/ was fabricated by anodic oxidation (anodization) of ultrathin Al films at room temperature in deionized water and then furnace annealed at 650/spl deg/C in N/sub 2/ ambient. Both dc and dac (dc superimposed with ac) anodization techniques were investigated. Effective dielectric constant of k/spl sim/7.5 and leakage current of 2-3 orders of magnitude lower than SiO/sub 2/ are observed. The conduction mechanism in Al/sub 2/O/sub 3/ gate stack is shown to be Fowler-Nordheim (F-N) tunneling. Saturated current behavior in the inversion region of MOS capacitor is observed. It is found that the saturation current is sensitive to interface state capacitance and can be used as an efficient way to evaluate the Al/sub 2/O/sub 3/ gate stack/Si-substrate interfacial property. An optimal process control for preparing Al/sub 2/O/sub 3/ gate dielectrics with minimized interface state capacitance via monitoring the inversion saturation current is demonstrated.

Stress effect on the kinetics of silicon thermal oxidation

Abstract: Oxidation of silicon wafers under external mechanical stress was studied in this work. From the oxide thickness profile measured by an automatic-scanning ellipsometer, it was found that the oxidation kinetics of silicon were significantly affected by mechanical stress. There are two distinct features of oxide thickness distribution corresponding to short and long times. By comparing the kinetic constants taken from experiments and the simulated stress distribution on the silicon wafer, we can possibly explain the two features of oxide thickness distribution: the initial rate constant is deformation dependent and the parabolic rate constant is stress dependent. The observed stress-dependent oxidation rates are important in the study of thin gate oxide reliability.

Ultrathin aluminum oxide gate dielectric on N-type 4H-SiC prepared by low thermal budget nitric acid oxidation

Abstract: MOS capacitors with an ultrathin aluminum oxide (Al/sub 2/O/sub 3/) gate dielectric were fabricated on n-type 4H-SiC. Al/sub 2/O/sub 3/ was prepared by room-temperature nitric acid (HNO/sub 3/) oxidation of ultrathin Al film followed by furnace annealing. The effective dielectric constant of k/spl sim/9.4 and equivalent oxide thickness of 26 /spl Aring/ are produced, and the interfacial layer and carbon clusters are not observed in this paper. The electrical responses of MOS capacitor under heating and illumination are used to identify the conduction mechanisms. For the positively biased case, the conduction mechanism is shown to be dominated by Schottky emission with an effective barrier height of 1.12/spl plusmn/0.13 eV. For the negatively biased case, the gate current is shown to be due to the generation-recombination process in depletion region and limited by the minority carrier generation rate. The feasibility of integrating alternative gate dielectric on SiC by a low thermal budget process is demonstrated.

High-k Al/sub 2/O/sub 3/ gate dielectrics prepared by oxidation of aluminum film in nitric acid followed by high-temperature annealing

Abstract: A simple, cost-effective, and room temperature process was proposed to prepare high-k gate dielectrics. An aluminum oxide (Al/sub 2/O/sub 3/) gate dielectric was prepared by oxidation of ultrathin Al film in nitric acid (HNO/sub 3/) at room temperature then followed by high-temperature annealing in O/sub 2/ or N/sub 2/. The substrate injection current behavior and interface trap-induced capacitance were introduced to investigate the interfacial property between the gate dielectric and Si substrate. Al/sub 2/O/sub 3/ gate dielectric MOS capacitors with and without initial SiO/sub 2/ layers were characterized. It was shown that the Al/sub 2/O/sub 3/ gate dielectrics with initial oxide exhibit better electrical properties than those without. The 650/spl deg/C N/sub 2/-POA Al/sub 2/O/sub 3/-SiO/sub 2/ sample with an equivalent oxide thickness of 18 /spl Aring/ exhibits three orders of magnitude reduction in gate leakage current in comparison with the conventional thermal SiO/sub 2/ sample.

Tantalum pentoxide (Ta2O5) thin films for advanced dielectric applications

Abstract: This paper reviews the present knowledge on tantalum pentoxide (Ta 2 O 5 ) thin films and their applications in the field of microelectronics and integrated microtechnologies. Different methods used to produce tantalum oxide layers are described, emphazing elaboration mechanisms and key parameters for each technique. We also review recent advances in the deposition of Ta 2 O 5 in the particular field of microelectronics where high quality layers are required from the structural and electrical points of view. The physical, structural, optical, chemical and electrical properties of tantalum oxide thin films on semiconductors are then presented and essential film parameters, such as optical index, film density or dielectric permittivity, are discussed. After a reminder of the basic mechanisms that control the bulk electrical conduction in insulating films, we carefully examine the origin of leakage currents in Ta 2 O 5 and present the state-of-the-art concerning the insulating behaviour of tantalum oxide layers. Finally, applications of tantalum oxide thin films are presented in the last part of this paper. We show how Ta 2 O 5 has been employed as an antireflection coating, insulating layer, gate oxide, corrosion resistant material, and sensitive layer in a wide variety of components, circuits and sensors.

Subject-Specific Finite Element Model of the Pelvis: Development, Validation and Sensitivity Studies

Abstract: A better understanding of the three-dimensional mechanics of the pelvis, at the patientspecific level, may lead to improved treatment modalities. Although finite element (FE) models of the pelvis have been developed, validation by direct comparison with subjectspecific strains has not been performed, and previous models used simplifying assumptions regarding geometry and material properties. The objectives of this study were to develop and validate a realistic FE model of the pelvis using subject-specific estimates of bone geometry, location-dependent cortical thickness and trabecular bone elastic modulus, and to assess the sensitivity of FE strain predictions to assumptions regarding cortical bone thickness as well as bone and cartilage material properties. A FE model of a cadaveric pelvis was created using subject-specific computed tomography image data. Acetabular loading was applied to the same pelvis using a prosthetic femoral stem in a fashion that could be easily duplicated in the computational model. Cortical bone strains were monitored with rosette strain gauges in ten locations on the left hemipelvis. FE strain predictions were compared directly with experimental results for validation. Overall, baseline FE predictions were strongly correlated with experimental resultssr 2 5 0.824d, with a best-fit line that was not statistically different than the line y 5 x sexperimental strains5 FE predicted strainsd. Changes to cortical bone thickness and elastic modulus had the largest effect on cortical bone strains. The FE model was less sensitive to changes in all other parameters. The methods developed and validated in this study will be useful for creating and analyzing patient-specific FE models to better understand the biomechanics of the pelvis.fDOI: 10.1115/1.1894148g

Review: Deposition of ceramic thin films at low temperatures from aqueous solutions

Abstract: Many techniques for the synthesis of ceramic thin films from aqueous solutions at low temperatures (25–100°C) have been reported. This paper reviews non-electrochemical, non-hydrothermal, low-temperature aqueous deposition routes, with an emphasis on oxide materials for electronic applications. Originally used for sulfide and selenide thin films, such techniques have also been applied to oxides since the 1970's. Films of single oxides (e.g., transition metal oxides, In2O3, SiO2, SnO2) and multicomponent films (doped ZnO, Cd2SnO4, ZrTiO4, ZrO2-Y2O3, Li-Co-O spinel, ferrites, perovskites) have been produced. The maximum thicknesses of the films obtained have ranged from 100 to 1000 nm, and deposition rates have ranged from 2 to 20,000 nm/h. Compared to vapor-deposition techniques, liquid-deposition routes offer lower capital equipment costs, lower processing temperatures, and flexibility in the choice of substrates with respect to topography and thermal stability. Compared to sol-gel techniques, the routes reviewed here offer lower processing temperatures, lower shrinkage, and (being based on aqueous precursors) lower costs and the potential for reduced environmental impact. This review emphasizes the influence of solution chemistry and process design on the microstructures and growth rates of the films. The current understanding of the mechanisms of film formation is presented, and the advantages and limitations of these techniques are discussed.

Radiation effects and hardening of MOS technology: devices and circuits

Abstract: Total ionizing dose radiation effects on the electrical properties of metal-oxide-semiconductor devices and integrated circuits are complex in nature and have changed much during decades of device evolution. These effects are caused by radiation-induced charge buildup in oxide and interfacial regions. This paper presents an overview of these radiation-induced effects, their dependencies, and the many different approaches to their mitigation.

Method for making a semiconductor device having a high-k gate dielectric

Abstract: A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.