Jeremy Buboltz

Bio: Jeremy Buboltz is an academic researcher from University of Central Florida. The author has contributed to research in topics: Network packet & Distributed Interactive Simulation. The author has an hindex of 1, co-authored 3 publications receiving 3 citations.

Front end device for content networking

Abstract: The bandwidth and speed of network connections are continually increasing. The speed increase in network technology is set to soon outpace the speed increase in CMOS technology. This asymmetrical growth is beginning to causing software applications that once worked with then current levels of network traffic to flounder under the new high data rates. Processes that were once executed in software now have to be executed, partially if not wholly in hardware. One such application that could benefit from hardware implementation is high layer routing. By allowing a network device to peer into higher layers of the OSI model, the device can scan for viruses, provide higher quality-of-service (QoS), and efficiently route packets. This paper proposes an architecture for a device that will utilize hardware-level string matching to distribute incoming requests for a server farm. The proposed architecture is implemented in VHDL, synthesized, and laid out on an Altera FPGA.

Performance Evaluation of Multi-Core Architectures in Training and Simulation: A Case Study with AMD and Intel Dual-Core Systems

Abstract: The defence training and simulation industry is increasingly using server CPUs for processing data. Distributed simulation data creates a large number of small packets that must be processed at the network level before the higher level simulation processing is performed. As network traffic increases it becomes a burden on the server CPUs, which need to process more packets and still have room for application software. Multi-core processor systems are being introduced as a solution to the increase in processor utilization. In this work, we evaluate the performance of servers based on the dual-core AMD Opteron and the dual-core Intel Xeon processors while executing in a typical distributed simulation environment. First, we illustrate the high processing power needed to process a network stream with small packet sizes. Second, we specify the differences between two major competitors in the server chip market, Intel's dual-core Xeon processor and AMD's dual-core Opteron processor. We then test the maximum thr...

An extensible, system-on-programmable-chip, content-aware Internet firewall

Abstract: An extensible firewall has been implemented that performs packet filtering, content scanning, and per-flow queuing of Internet packets at Gigabit/second rates The firewall uses layered protocol wrappers to parse the content of Internet data Packet payloads are scanned for keywords using parallel regular expression matching circuits Packet headers are compared to rules specified in Ternary Content Addressable Memories (TCAMs) Per-flow queuing is performed to mitigate the effect of Denial of Service attacks All packet processing operations were implemented with reconfigurable hardware and fit within a single Xilinx Virtex XCV2000E Field Programmable Gate Array (FPGA) The single-chip firewall has been used to filter Internet SPAM and to guard against several types of network intrusion Additional features were implemented in extensible hardware modules deployed using run-time reconfiguration

Implementation of Compressed Brute-Force Pattern Search Algorithm Using VHDL

Abstract: High speed and always-on network access is becoming commonplace around the world, creating a demand for increased network security. Network Intrusion Detection Systems (NIDS) attempt to detect and prevent attacks from the network using pattern-matching rules. Data compression methods are used to reduce the data storage requirement. Searching a compressed pattern in the compressed text reduces the internal storage requirement and computation resources. In this paper we implemented search process to perform compressed pattern matching in binary Huffman encoded texts. Brute-Force Search algorithm is applied comparing a single bit per clock cycle and comparing an encoded character per clock cycle. Pattern matching processes are evaluated in terms of clock cycle.