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Jerome Billoue

Bio: Jerome Billoue is an academic researcher from François Rabelais University. The author has contributed to research in topics: Silicon & Porous silicon. The author has an hindex of 11, co-authored 34 publications receiving 257 citations. Previous affiliations of Jerome Billoue include Intelligence and National Security Alliance.

Papers
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Journal ArticleDOI
TL;DR: In this paper, the effect of various n-type substrates on high-frequency inductor performances was investigated and several devices were integrated on porous silicon (PS), silicon (Si), and glass.
Abstract: To study the effect of various n-type substrates on high-frequency inductor performances, several devices were integrated on porous silicon (PS), silicon (Si), and glass. Both n-type mesoporous Si and mesoporous/macroporous Si bilayers were fabricated. The analysis further shows that PS reduces significantly the substrate losses. Indeed, higher quality factors have been obtained for the inductors integrated on PS than on the Si substrate and particularly in the case of bilayer structures. These original results can be added to p-type PS performances already shown in the literature. Then, this work demonstrates that PS can also be a promising candidate for the integration of passive and active devices on n-type silicon.

29 citations

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TL;DR: Electrochemical anodization of n-type heavily doped 4 H-SiC wafers in a HF-based electrolyte without any UV light assistance is studied to present the differences observed between the etching of Si and C faces.
Abstract: In this paper, we study the electrochemical anodization of n-type heavily doped 4 H-SiC wafers in a HF-based electrolyte without any UV light assistance. We present, in particular, the differences observed between the etching of Si and C faces. In the case of the Si face, the resulting material is mesoporous (diameters in the range of 5 to 50 nm) with an increase of the ‘chevron shaped’ pore density with depth. In the case of the C face, a columnar morphology is observed, and the etch rate is twice greater than for the one for the Si face. We've also observed the evolution of the potential for a fixed applied current density. Finally, some wafer defects induced by polishing are clearly revealed at the sample surfaces even for very short etching times.

27 citations

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TL;DR: A novel strong, resistant fluoropolymer mask is introduced to localize the porous silicon on the silicon wafer and shows that the localized porous silicon substrate significantly reduces losses in comparison with high-resistivity silicon or highly doped silicon bulks.
Abstract: To study the influence of localized porous silicon regions on radiofrequency performances of passive devices, inductors were integrated on localized porous silicon regions, full porous silicon sheet, bulk silicon and glass substrates. In this work, a novel strong, resistant fluoropolymer mask is introduced to localize the porous silicon on the silicon wafer. Then, the quality factors and resonant frequencies obtained with the different substrates are presented. A first comparison is done between the performances of inductors integrated on same-thickness localized and full porous silicon sheet layers. The effect of the silicon regions in the decrease of performances of localized porous silicon is discussed. Then, the study shows that the localized porous silicon substrate significantly reduces losses in comparison with high-resistivity silicon or highly doped silicon bulks. These results are promising for the integration of both passive and active devices on the same silicon/porous silicon hybrid substrate.

24 citations

Journal ArticleDOI
TL;DR: In this paper, the authors presented electrochemical etching conditions to obtain thick mesoporous silicon electrical insulating layers for RF applications from high resistivity substrates (30-50 µm).
Abstract: In this paper, we present electrochemical etching conditions to obtain thick mesoporous silicon electrical insulating layers for RF applications from high resistivity substrates (30–50 Ω cm). We present the realization and the characterization of spiral inductors on thick mesoporous silicon layers. Indeed, PSi layers reduce significantly the resistive and capacitive losses of the substrate, so, quality factor and resonant frequencies are improved for integrated inductors. In complement, we develop the integration of such devices in notch filters and we show the first measurement results on 100 µm thick mesoporous silicon layers.

21 citations

Journal ArticleDOI
18 Sep 2015
TL;DR: The evolution of porous silicon from its early studies in the late 70's toward its industrial application in microelectronics is described in this article, where the authors put an emphasis on reproducibility and homogeneity issues, on the wafer warp management using different annealing procedures.
Abstract: The evolution of porous silicon (PSi) from its early studies in the late 70's toward its industrial application in microelectronics is described in this article. The way this material can be integrated now in many devices at a wafer level is shown in this paper through examples of prototypes that include PSi in their fabrication process. For instance, realization of devices on large area wafers in the field of RF passive components, energy micro-sources or porous flexible membranes are described. In this paper, we also show recent advances in the field of PSi etching and integration at an industrial level. In particular, we put an emphasis on reproducibility and homogeneity issues, on the wafer warp management using different annealing procedures.

19 citations


Cited by
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01 Jan 1999
TL;DR: Damascene copper electroplating for on-chip interconnections, a process that was conceived and developed in the early 1990s, makes it possible to fill submicron trenches and vias with copper without creating a void or a seam and has thus proven superior to other technologies of copper deposition as discussed by the authors.
Abstract: Damascene copper electroplating for on-chip interconnections, a process that we conceived and developed in the early 1990s, makes it possible to fill submicron trenches and vias with copper without creating a void or a seam and has thus proven superior to other technologies of copper deposition. We discuss here the relationship of additives in the plating bath to superfilling, the phenomenon that results in superconformal coverage, and we present a numerical model which accounts for the experimentally observed profile evolution of the plated metal.

1,006 citations

Journal ArticleDOI
TL;DR: In this article, a comprehensive overview on the designed growth of one-dimensional (1D) SiC nanostructures in fruitful morphologies with tailored doping is presented, followed by a detailed discussion to highlight a range of intriguing properties.

102 citations

Journal ArticleDOI
TL;DR: An overview of the development of Co-based hard and semi-hard magnetic materials and their intrinsic and extrinsic magnetic properties in view of fundamental understanding and technological applications can be found in this paper.

45 citations

Journal ArticleDOI
TL;DR: It was shown that the dielectric parameters of porous Si (dielectric permittivity and loss tangent) in the above frequency range have values similar to those obtained at lower frequencies (1 to 40 GHz).
Abstract: In this work, the dielectric properties of porous Si for its use as a local substrate material for the integration on the Si wafer of millimeter-wave devices were investigated in the frequency range 140 to 210 GHz. Broadband electrical characterization of coplanar waveguide transmission lines (CPW TLines), formed on the porous Si layer, was used in this respect. It was shown that the dielectric parameters of porous Si (dielectric permittivity and loss tangent) in the above frequency range have values similar to those obtained at lower frequencies (1 to 40 GHz). More specifically, for the samples used, the obtained values were approximately 3.12 ± 0.05 and 0.023 ± 0.005, respectively. Finally, a comparison was made between the performance of the CPW TLines on a 150-μm-thick porous Si layer and on three other radiofrequency (RF) substrates, namely, on trap-rich high-resistivity Si (trap-rich HR Si), on a standard complementary metal-oxide-semiconductor (CMOS) Si wafer (p-type, resistivity 1 to 10 Ω.cm) and on quartz. 84.40.-x; 77.22.Ch; 81.05.Rm

44 citations

Journal ArticleDOI
TL;DR: In this article, the porosities between 70% and 84% of the investigated coplanar waveguide transmission lines were found to be Q=26 and a=0.19ndB/mm, respectively, at 40 GHz.
Abstract: Dielectric permittivity of porous Si (PSi) layers formed on a low-resistivity p-type Si (0.001-0.005 Ω.cm) is thoroughly investigated using analytical expressions within the frame of broadband transmission line characterization method in the frequency range 1-40 GHz. It is demonstrated that the value of Si resistivity is critical for the resulting PSi layer permittivity even within the above limited resistivity range. The real part of PSi dielectric permittivity changes monotonically between 1.8 and 4 by changing the Si resistivity between 0.001 and 0.005 Ω.cm. The above study was made for porosities between 70% and 84%. The quality factor and attenuation loss of the investigated coplanar waveguide transmission lines were found to be Q=26 and a=0.19ndB/mm, respectively, at 40 GHz. These values are competitive to those obtained on quartz, which is one of the off-chip RF substrates with the lowest losses. This confirms the superiority of the PSi material, mentioned above, for use as a local substrate for the on-chip RF device integration.

39 citations