J
Jerome Mitard
Researcher at Katholieke Universiteit Leuven
Publications - 274
Citations - 3849
Jerome Mitard is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: Electron mobility & MOSFET. The author has an hindex of 29, co-authored 263 publications receiving 3326 citations. Previous affiliations of Jerome Mitard include IMEC.
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Journal ArticleDOI
Germanium MOSFET Devices: Advances in Materials Understanding, Process Development, and Electrical Performance
David P. Brunco,B. De Jaeger,Geert Eneman,Jerome Mitard,Geert Hellings,Alessandra Satta,Valentina Terzieva,Laurent Souriau,Frederik Leys,Geoffrey Pourtois,Michel Houssa,Gillis Winderickx,E. Vrancken,Sonja Sioncke,Karl Opsomer,G. Nicholas,Matty Caymax,Andre Stesmans,J. Van Steenbergen,Paul W. Mertens,Marc Meuris,M.M. Heyns +21 more
TL;DR: In this article, thin, strained epi-Si is examined as a passivation of the Ge/gate dielectric interface, with an optimized thickness found at 6 monolayers.
Journal ArticleDOI
SiGe Channel Technology: Superior Reliability Toward Ultrathin EOT Devices—Part I: NBTI
Jacopo Franco,B. Kaczer,Philippe Roussel,Jerome Mitard,Moonju Cho,Liesbeth Witters,Tibor Grasser,Guido Groeseneken +7 more
TL;DR: In this article, the negative bias temperature instability (NBTI) reliability of SiGe channel pMOSFETs as a function of the main gate-stack parameters was investigated.
Journal ArticleDOI
Electrical TCAD Simulations of a Germanium pMOSFET Technology
Geert Hellings,Geert Eneman,Raymond Krom,B. De Jaeger,Jerome Mitard,An De Keersgieter,Thomas Hoffmann,Marc Meuris,Kristin De Meyer +8 more
TL;DR: In this paper, a commercial technology computer-aided design device simulator was extended to allow electrical simulations of sub-100-nm germanium pMOSFETs, and parameters for generation/recombination mechanisms (Shockley-Read-Hall, trap-assisted tunneling, and band-to-band tunneling) and mobility models (impurity scattering and mobility reduction at high lateral and transversal field) were provided.
Proceedings ArticleDOI
Record I ON /I OFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability
Jerome Mitard,B. De Jaeger,Frederik Leys,Geert Hellings,Koen Martens,Geert Eneman,David P. Brunco,Roger Loo,Jing-Cheng Lin,Denis Shamiryan,T. Vandeweyer,Gillis Winderickx,E. Vrancken,C.H. Yu,K. De Meyer,Matty Caymax,Luigi Pantisano,Marc Meuris,M.M. Heyns +18 more
TL;DR: In this paper, a 65 nm Ge pFET with a record performance of Ion = 478muA/mum and Ioff,s= 37nA /mum @Vdd= -1V.
Proceedings ArticleDOI
An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates
Niamh Waldron,Clement Merckling,W. Guo,Patrick Ong,Lieve Teugels,S. Ansar,Diana Tsvetanova,Farid Sebaai,D. H. van Dorp,Alexey Milenin,D. Lin,Laura Nyns,Jerome Mitard,Ali Pourghaderi,Bastien Douhard,O. Richard,Hugo Bender,Guillaume Boccardi,Matty Caymax,M.M. Heyns,Wilfried Vandervorst,Kathy Barla,Nadine Collaert,A. V-Y. Thean +23 more
TL;DR: In this article, a Si-IIIV hybrid 300mm R&D pilot line is demonstrated with InGaAs FinFETs with a SS of 190 mV/dec and extrinsic gm of 558 μS/μm for an EOT of 1.9nm, L g of 50nm and fin width of 55nm.