This brief presents a temperature sensor operating over a wide temperature range from 25°C to 225°C for oil well instrumentation applications. The temperature sensor is implemented with a simple time-domain architecture and a mapping function at the digital back end. The mapping function eliminates the need for a band-gap reference, whose temperature coefficient deteriorates the accuracy, particularly for high and wide temperature range of operation. The time-domain implementation results in low power consumption and chip area. With digital calibration at room temperature using a field-programmable gate array, the sensor achieves a worst case inaccuracy of +1.6 °C/−1.5 °C and consumes only 20- $\mu$ A current under a 4.5-V supply. The chip is fabricated with a commercial partially depleted silicon-on-insulator CMOS process and occupies a chip area of 0.41 mm2.

A Time-Domain Band-Gap Temperature Sensor in SOI CMOS for High-Temperature Applications

This article presents a BJT-based temperature-to-digital-converter (TDC) that achieves ±0.25 °C 3 $\sigma $ -inaccuracy from −40 °C to +180 °C after a heater-assisted voltage calibration (HA-VCAL). Its switched-capacitor (SC) ADC employs two sampling capacitors and, thus, the minimum number of critical sampling switches, which minimizes the effects of switch leakage at high temperatures and improves accuracy. The TDC is also equipped with an on-chip heater, with which the sensing BJTs can be rapidly ( $\mu \text {m}$ standard CMOS, the TDC, including the on-chip heater, occupies 0.15 mm2 and operates from 1.8 V.

/pdf/a-bjt-based-temperature-to-digital-converter-with-a-0-25-c-3-1wvl9y5d7s.pdf

A BJT-Based Temperature-to-Digital Converter With a ±0.25 °C 3 $\sigma$ -Inaccuracy From −40 °C to +180 °C Using Heater-Assisted Voltage Calibration

We describe a Complementary Metal-Oxide Semiconductor (CMOS) differential interface circuit for capacitive Micro-Electro-Mechanical Systems (MEMS) pressure sensors that is functional over a wide temperature range between −55 °C and 225 °C. The circuit is implemented using IBM 0.13 μm CMOS technology with 2.5 V power supply. A constant-gm biasing technique is used to mitigate performance degradation at high temperatures. The circuit offers the flexibility to interface with MEMS sensors with a wide range of the steady-state capacitance values from 0.5 pF to 10 pF. Simulation results show that the circuitry has excellent linearity and stability over the wide temperature range. Experimental results confirm that the temperature effects on the circuitry are small, with an overall linearity error around 2%.

https://www.mdpi.com/1424-8220/15/2/4253/pdf

Differential Wide Temperature Range CMOS Interface Circuit for Capacitive MEMS Pressure Sensors

This work focuses on analog integrated CMOS (Complementary Metal-Oxide-Semiconductor) circuit design in SOI (Silicon on Insulator) technology for the use in high temperature applications It investigates the influence of reverse body biasing (RBB) on the analog characteristics of SOI-MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) transistors Additionally, the enhancement of the operation capability of fundamental analog circuits at high temperatures up to 400°C with the use of RBB is investigated
Analog and digital integrated circuits are used in a variety of applications, eg consumer electronics or industrial measurement equipment These integrated circuits have to work properly in the temperature range predefined by the application As an example, operating temperatures reaching from −50°C to 250°C are required for geothermal drilling applications Currently in the automotive industry, electronics have to operate reliably up to 150°C and as control electronics are placed closer to the engine, a much higher operating temperature is required High temperature electronics are also used in avionic- and space applications, eg for future Venus exploration missions, where they have to withstand operating temperatures of 300°C to 500°C Active or passive cooling of electronic components requires additional space and weight that increases the cost of the overall system Cooling can be avoided in case electronics are capable of operating in harsh environmental conditions, ie at high temperatures
SOI-MOSFET devices are theoretically capable of operation up to 400°C or even higher, depending on the doping concentration of the silicon film Nearly all material and device properties of importance to electronics worsen with increasing temperature, which is why 300°C to 350°C is the currently stated experimental maximum operating temperature of SOI devices Analog circuit design up to the theoretical temperature limit exhibits severe limitations as SOI-MOSFET device characteristics are degenerated SOI-MOSFET devices are partially depleted (PD) or fully depleted (FD), depending on the temperature, doping concentration of the silicon film, silicon film thickness and also channel length FD devices offer a much better analog performance compared to their partially depleted counterparts and are preferred for analog circuit design In the considered SOI technology, SOI- MOSFET devices are FD at low temperatures and PD at high temperatures The transition from FD to PD at high temperatures leads to increased device leakage currents and hence reduces the overall performance of the transistor devices
Thereby, the gm/Id factor as a major figure of merit is decreased dramatically at high temperatures Especially the moderate inversion region, which offers high intrinsic gain and moderate intrinsic bandwidth, is strongly affected as device leakage currents exceed the range of device operating currents at high temperatures Reverse body biasing (RBB) refers to the reverse biasing of the film-source PN-junction of a MOSFET transistor In recent works, reverse body biasing has been applied to digital circuits in order to reduce the static current consumption Reverse body biasing has also been investigated in the analog domain Nevertheless, the importance of the technique to realize analog circuits capable of operating at the theoretical temperature limit of SOI technology has not been identified yet SOI-MOSFET devices with an H-shaped gate are investigated in a 10 µm PD-SOI technology These devices provide a body-contact, which is used to apply the reverse body bias It is found that due to the use of RBB, these devices remain fully depleted in the considered temperature range up to 400°C Due to the reduction of leakage currents, reverse biased SOI-MOSFET devices are capable of operating in the mid moderate inversion region, with an operating current of one fifth of the leakage current level which was measured without RBB This results in an improved gm/Id factor and an increase of the intrinsic gain by approximately 14 dB Besides the investigation of SOI-MOSFET device characteristics, reverse body biasing is also applied to fundamental analog building blocks, eg an analog switch, current mirrors, a two-stage operational amplifier and a first order bandgap voltage reference It is found that reverse body biasing significantly improves the high temperature operation of these circuits In summary, the proposed technique of reverse body biasing offers the possibility to achieve FD device characteristics in a PD-SOI technology and thereby to improve the performance of analog circuits at high temperatures up to 400°C

Analog Circuit Design in PD-SOI CMOS Technology for High Temperatures up to 400°C using Reverse Body Biasing (RBB)

This paper investigates the concepts, performance and limitations of temperature sensing circuits realized in complementary metal-oxide-semiconductor (CMOS) silicon on insulator (SOI) technology. It is shown that the MOSFET threshold voltage (Vt) can be used to accurately measure the chip local temperature by using a Vt extractor circuit. Furthermore, the circuit's performance is compared to standard circuits used to generate an accurate output current or voltage proportional to the absolute temperature, i.e., proportional-to-absolute temperature (PTAT), in terms of linearity, sensitivity, power consumption, speed, accuracy and calibration needs. It is shown that the Vt extractor circuit is a better solution to determine the temperature of low power, analog and mixed-signal designs due to its accuracy, low power consumption and no need for calibration. The circuit has been designed using 1 µm partially depleted (PD) CMOS-SOI technology, and demonstrates a measurement inaccuracy of ±1.5 K across 300 K⁻500 K temperature range while consuming only 30 µW during operation.

https://www.mdpi.com/1424-8220/18/5/1629/pdf

Study of CMOS-SOI Integrated Temperature Sensing Circuits for On-Chip Temperature Monitoring.

For sample-and-hold (S/H) circuits operating at low sampling rate and high temperature, the switch leakage current is one of the major error sources. A S/H circuit with dynamic switch leakage compensation is presented. The proposed leakage current compensation circuit generates switch leakage replicas that track the actual leakages in the sampling switches. A bidirectional current steering circuit allows the switch leakage to be dynamically compensated with the leakage replicas. A prototype S/H circuit is fabricated in a 1 μm silicon-on-isolation CMOS technology. Measurement has shown the effectiveness of dynamic leakage current compensation up to 280°C with a maximum 75% leakage reduction.

https://ietresearch.onlinelibrary.wiley.com/doi/pdf/10.1049/el.2013.2092

Sample-and-hold circuit with dynamic switch leakage compensation

This brief presents a complementary-to-absolute-temperature voltage and a voltage reference based on the threshold voltage Vth extraction principle. The proposed Vth extraction circuit eliminates the nonlinear temperature-dependent mobility and mobility ratio terms, and it achieves a wide operating temperature range from -25 °C to 250 °C. The threshold-voltage temperature coefficient (TC) mismatch between nMOS and pMOS is compensated by selecting different channel lengths. Fabricated in the 1-μm partially depleted silicon-on-insulator CMOS process, the voltage reference achieves a box model TC of 27 parts per million (ppm) (mean) for an operating temperature range of -25 °C-250 °C and 18.7 ppm (mean) for a range of 25 °C-150 °C. Furthermore, the ratiometric output achieves mean temperature inaccuracy within ±1.8% over a temperature of 275 °C.

Temperature Sensor Front End in SOI CMOS Operating up to 250

Decreasing reliability of nanometer CMOS technologies with each technology generation is a bottleneck for development of dependable Cyber Physical Systems. This paper presents two analogue health monitors, namely IDDT and temperature along with their integration to the IJTAG network for MPSoC life-time prediction. The monitors are integrated as embedded instruments in a MPSoC. A technique for dynamic synthesis of the analogue front-end for the IDDT instrument and an architecture for integrating analogue embedded instruments into an IJTAG network is introduced in this paper. The embedded instruments have been designed in TSMC 40nm CMOS technology.

IJTAG compatible analogue embedded instruments for MPSoC life-time prediction

This paper describes a bandgap reference with temperature range up to 300°C. Fabricated in a PDSOI CMOS technology, the bandgap reference achieves a box model temperature coefficient of 138ppm from 25 to 300°C, and line regulation less than 1.5mv/V. The minimum operating voltage is 2V and consumes merely 285μW at room temperature over several samples.

Jerrin Pathrose

Papers

A Time-Domain Band-Gap Temperature Sensor in SOI CMOS for High-Temperature Applications

Sample-and-hold circuit with dynamic switch leakage compensation

Temperature Sensor Front End in SOI CMOS Operating up to 250

IJTAG compatible analogue embedded instruments for MPSoC life-time prediction

High temperature bandgap reference in PDSOI CMOS with operating temperature up to 300°C