Multiprocessor Systems-on-Chip (MPSoCs) is a trend in VLSI design, since they minimize the "design crisis " (gap between silicon technology and actual SoC design capacity) and reduce the time to market. Important issues in MPSoC design are the communication infrastructure and task mapping. MPSoCs may employ NoCs to integrate multiple programmable processor cores, specialized memories, and other IPs in a scalable way. Applications running in MPSoCs execute a varying number of tasks simultaneously, and their number may exceed the available resources, requiring task mapping to be executed at runtime to meet real-time constraints. Most works in the literature present static MPSoC mapping solutions. Static mapping defines a fixed placement and scheduling, not appropriate for dynamic workloads. Task migration has also been proposed for use in MPSoCs, with the goal to relocate tasks when performance bottlenecks are identified. This work investigates the performance of mapping heuristics in NoC-based MPSoCs with dynamic workloads, targeting NoC congestion minimization, a key cost function to optimize the NoC performance. Here, tasks are mapped on the fly, according to communication requests and the load in the NoC links. Results show execution time and congestion reduction when congestion-aware mapping heuristics are employed.

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Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs

Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications.

Field Programmable Gate Array Applications—A Scientometric Review

Partially reconfigurable devices allow to configure and execute tasks in a true multitasking manner The main characteristics of mapping tasks to such devices is the strong nexus between scheduling and placement In this paper, we formulate a new online real-time scheduling problem and present two heuristics, the horizon and the stuffing technique, to tackle it Simulation experiments evaluate the performance and the runtime efficiency of the schedulers Finally, we discuss our prototyping work toward an integration of scheduling and placement into an operating system for reconfigurable devices

Heuristics for online scheduling real-time tasks to partially reconfigurable devices

We describe algorithmic results on two crucial aspects of allocating resources on computational hardware devices with partial reconfigurability. By using methods from the field of computational geometry, we derive a method that allows correct maintenance of free and occupied space of a set of n rectangular modules in time O(n log n); previous approaches needed a time of O(n2) for correct results and O(n) for heuristic results. We also show a matching lower bound of Omega (n log n), so our approach is optimal. We also show that finding an optimal feasible communication-conscious placement (which minimizes the total weighted Manhattan distance between the new module and existing demand points) can be computed with Theta(n log n). Both resulting algorithms are practically easy to implement and show convincing experimental behavior

Optimal Free-Space Management and Routing-Conscious Dynamic Placement for Reconfigurable Devices

Static scheduling techniques for dependent tasks on dynamically reconfigurable devices

A novel technique is proposed for the management of a two-dimensional run-time reconfigurable device in order to get true hardware multitasking. The proposed technique uses a Vertex List Set to keep track of the available free area, and of the candidate locations to place the arriving tasks. Each Vertex List describes the contour of each unoccupied area fragment in the reconfigurable device. Several heuristics are proposed to solve the problem of selecting one of the vertices to place the task. The heuristic that gives best results is based on a novel fragmentation metric. This metric estimates for each alternative location the suitability of the resulting free device area to accept future incoming tasks. Finally, we show that our approach, with a reasonable complexity, gives better results, in terms of device fragmentation and efficiency, than other techniques.

A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management

To get efficient HW management in 2D reconfigurable systems, heuristics are needed to select the best place to locate each arriving task. We propose a technique that locates the task next to the borders of the free area for as many cycles as possible, trying to minimize the area fragmentation. Moreover, we combine it with a look-ahead heuristic that allows delaying the scheduling of a task to the next event, increasing the solution search space.

Task placement heuristics based on 3D-adjacency and look-ahead in reconfigurable systems

This paper presents the structure, design and implementation of a new adaptive digital shaper for processing the pulses generated in nuclear particle detectors. The proposed adaptive algorithm has the capacity to automatically adjust the coefficients for shaping an input signal with a desired profile in real-time. Typical shapers such as triangular, trapezoidal or cusp-like ones can be generated, but more exotic unipolar shaping could also be performed. A practical prototype was designed, implemented and tested in a Field Programmable Gate Array (FPGA). Particular attention was paid to the amount of internal FPGA resources required and to the sampling rate, making the design as simple as possible in order to minimize power consumption. Lastly, its performance and capabilities were measured using simulations and a real benchmark.

Implementation of a real-time adaptive digital shaping for nuclear spectroscopy

This paper focuses on the fragmentation problem produced in 2D run-time reconfigurable FPGAs when hardware multitasking management is considered. Though allocation heuristics can take fragmentation into account when a new task arrives, the free area becomes inevitably fragmented as the tasks finish and exit the FPGA. The main contributions of our work are a fragmentation metric able to estimate when the FPGA fragmentation status has become critical, and several heuristics to decide when to perform defragmentation and how to perform it. This defragmentation heuristics can be of a preventive kind, driven by alarms that fire when isolated islands appear or a high fragmentation status is reached. It can be also an on-demand process produced when a task allocation fails though there is enough free area in the FPGA to accommodate it.

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2D defragmentation heuristics for hardware multitasking on reconfigurable devices

Plans to launch miniaturized satellite missions have been increasing in the last few years. Space missions like these are exposed to radiation, which is a cause of errors in electronic systems. Memories are one of the electronic systems that need special attention. Radiation effects in memories include single-event upsets (SEUs), multiple cell upsets, and single-event functional interrupts (SEFIs). In this paper, two solutions are presented to protect a nano/pico satellite onboard computer memory prototype with 16-bit data words against SEFIs and SEUs. The prototype uses a 32-bit memory interface, organized in two 16-bit chips. The approach to provide the error-correction capabilities is based on orthogonal latin square codes. The results show that the area and delay introduced by the solutions are acceptable. When a SEFI affects one of the chips, the solutions are able to recover the information using the remaining data.

Jesús Tabero

Papers

A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management

Task placement heuristics based on 3D-adjacency and look-ahead in reconfigurable systems

Implementation of a real-time adaptive digital shaping for nuclear spectroscopy

2D defragmentation heuristics for hardware multitasking on reconfigurable devices

SEFI Protection for Nanosat 16-Bit Chip Onboard Computer Memories