Ji-Jon Sit

Bio: Ji-Jon Sit is an academic researcher from Massachusetts Institute of Technology. The author has contributed to research in topics: Communication channel & Microphone. The author has an hindex of 9, co-authored 15 publications receiving 577 citations.

An ultra-low-power programmable analog bionic ear processor

Abstract: We report a programmable analog bionic ear (cochlear implant) processor in a 1.5-/spl mu/m BiCMOS technology with a power consumption of 211 /spl mu/W and 77-dB dynamic range of operation. The 9.58 mm/spl times/9.23 mm processor chip runs on a 2.8 V supply and has a power consumption that is lower than state-of-the-art analog-to-digital (A/D)-then-DSP designs by a factor of 25. It is suitable for use in fully implanted cochlear-implant systems of the future which require decades of operation on a 100-mAh rechargeable battery with a finite number of charge-discharge cycles. It may also be used as an ultra-low-power spectrum-analysis front end in portable speech-recognition systems. The power consumption of the processor includes the 100 /spl mu/W power consumption of a JFET-buffered electret microphone and an associated on-chip microphone front end. An automatic gain control circuit compresses the 77-dB input dynamic range into a narrower internal dynamic range (IDR) of 57 dB at which each of the 16 spectral channels of the processor operate. The output bits of the processor are scanned and reported off chip in a format suitable for continuous-interleaved-sampling stimulation of electrodes. Power-supply-immune biasing circuits ensure robust operation of the processor in the high-RF-noise environment typical of cochlear implant systems.

A Low-Power Blocking-Capacitor-Free Charge-Balanced Electrode-Stimulator Chip With Less Than 6 nA DC Error for 1-mA Full-Scale Stimulation

Abstract: Large dc blocking capacitors are a bottleneck in reducing the size and cost of neural implants. We describe an electrode-stimulator chip that removes the need for large dc blocking capacitors in neural implants by achieving precise charge-balanced stimulation with <6 nA of dc error. For cochlear implant patients, this is well below the industry's safety limit of 25 nA. Charge balance is achieved by dynamic current balancing to reduce the mismatch between the positive and negative phases of current to 0.4%, followed by a shorting phase of at least 1 ms between current pulses to further reduce the charge error. On +6 and -9 V rails in a 0.7-mum AMI high voltage process, the power consumption of a single channel of this chip is 47 muW when biasing power is shared by 16 channels.

An analog bionic ear processor with zero-crossing detection

Abstract: A 75 dB 251 /spl mu/W analog speech processor is described that preserves the performance, robustness, and programmability needed for deaf patients at a reduced power consumption compared to that of implementations with A/D and DSP. It also provides zero-crossing outputs for stimulation strategies that use phase information to improve performance.

A Low-Power Asynchronous Interleaved Sampling Algorithm for Cochlear Implants That Encodes Envelope and Phase Information

Abstract: Cochlear implants currently fail to convey phase information, which is important for perceiving music, tonal languages, and for hearing in noisy environments. We propose a bio-inspired asynchronous interleaved sampling (AIS) algorithm that encodes both envelope and phase information, in a manner that may be suitable for delivery to cochlear implant users. Like standard continuous interleaved sampling (CIS) strategies, AIS naturally meets the interleaved-firing requirement, which is to stimulate only one electrode at a time, minimizing electrode interactions. The majority of interspike intervals are distributed over 1-4 ms, thus staying within the absolute refractory limit of neurons, and form a more natural, pseudostochastic pattern of firing due to complex channel interactions. Stronger channels are selected to fire more often but the strategy ensures that weaker channels are selected to fire in proportion to their signal strength as well. The resulting stimulation rates are considerably lower than those of most modern implants, saving power yet delivering higher potential performance. Correlations with original sounds were found to be significantly higher in AIS reconstructions than in signal reconstructions using only envelope information. Two perceptual tests on normal-hearing listeners verified that the reconstructed signals enabled better melody and speech recognition in noise than those processed using tone-excited envelope-vocoder simulations of cochlear implant processing. Thus, our strategy could potentially save power and improve hearing performance in cochlear implant users

A micropower logarithmic A/D with offset and temperature compensation

Abstract: Logarithmic circuits are useful in many applications that require nonlinear signal compression, such as in speech recognition front-ends (SRFEs) and cochlear implants or bionic ears (BEs). A logarithmic current-input analog-to-digital converter (A/D) with temperature compensation and automatic offset calibration is presented in this paper. It employs a diode to compute the logarithm, a wide linear range transconductor to perform voltage-to-current conversion, and a dual-slope auto- zeroing topology with 60 dB of dynamic range for sampling the envelope of speech signals. The temperature dependence of the logarithm inherent in a diode implementation is automatically cancelled in our circuit topology. Experimental results from a 1.5-/spl mu/m 3-V BiCMOS process show that the converter achieves a temperature stability lower than 150 ppm//spl deg/C from 12/spl deg/C to 42/spl deg/C, and consumes only 3 /spl mu/W of power when sampling at 300 Hz. At this level of power consumption, we show that the design is thermal-noise limited to 8 bits of precision. This level of precision is more than adequate for deaf patients and for speech recognition front-ends. The power consumption is almost two orders of magnitude lower than state-of-the-art DSP implementations, and the use of a local feedback topology achieves a 2.5-bit improvement over conventional dual-slope designs.

Implantable Transponder Systems and Methods

Abstract: A method and system for providing electrical stimulation to tissue includes implanting one or more battery-free microtransponders having spiral antennas into tissue. Energy is provided wirelessly to the plurality of microtransponders. Tissue is stimulated using the energy.

On Spike-Timing-Dependent-Plasticity, Memristive Devices, and Building a Self-Learning Visual Cortex

Abstract: In this paper we present a very exciting overlap between emergent nano technology and neuroscience. We are linking one type of memristor nano technology devices to the biological synaptic update rule known as Spike-Time-Dependent-Plasticity found in real biological synapses. Understanding this link allows neuromorphic engineers to develop circuit architectures that use this type of memristors to artificially emulate parts of the visual cortex. We focus on the type of memristors referred to as voltage driven memristors and focus our discussions on a behavioral macro model for such devices. The implementations result in fully asynchronous architectures with neurons sending their action potentials not only forwards but also backwards. One critical aspect is to use neurons that generate spikes of specific shapes. By changing the shapes of the neuron action potential spikes we can tune and manipulate the STDP learning rules for both excitatory and inhibitory synapses. We show how neurons and memristors can be interconnected to achieve large scale spiking learning systems, that follow a type of multiplicative STDP learning rule. We briefly extend the architectures to use three-terminal transistors with similar memristive behavior. We illustrate how a V1 visual cortex layer can assembled and how it is capable of learning to extract orientations from visual data coming from a real artificial CMOS spiking retina observing real life scenes. Finally, we discuss limitations of currently available memristors. The results presented are based on behavioral simulations and do not take into account non-idealities of devices and interconnects. The aim of this paper is to present, in a tutorial manner, an initial framework for the possible development of fully asynchronous STDP learning neuromorphic architectures exploiting two or three terminal memristive type devices. All files used for the simulations are made available through the journal web site.

Feedback Analysis and Design of RF Power Links for Low-Power Bionic Systems

Abstract: This paper presents a feedback-loop technique for analyzing and designing RF power links for transcutaneous bionic systems, i.e., between an external RF coil and an internal RF coil implanted inside the body. The feedback techniques shed geometric insight into link design and minimize algebraic manipulations. We demonstrate that when the loop transmission of the link's feedback loop is -1, the link is critically coupled, i.e., the magnitude of the voltage transfer function across the link is maximal. We also derive an optimal loading condition that maximizes the energy efficiency of the link and use it as a basis for our link design. We present an example of a bionic implant system designed for load power consumptions in the 1-10-mW range, a low-power regime not significantly explored in prior designs. Such low power levels add to the challenge of link efficiency, because the overhead associated with switching losses in power amplifiers at the link input and with rectifiers at the link output significantly degrade link efficiency. We describe a novel integrated Class-E power amplifier design that uses a simple control strategy to minimize such losses. At 10-mW load power consumption, we measure overall link efficiencies of 74% and 54% at 1- and 10-mm coil separations, respectively, in good agreement with our theoretical predictions of the link's efficiency. At 1-mW load power consumption, we measure link efficiencies of 67% and 51% at 1- and 10-mm coil separations, respectively, also in good accord with our theoretical predictions. In both cases, the link's rectified output dc voltage varied by less than 16% over link distances that ranged from 2 to 10 mm

STDP and STDP variations with memristors for spiking neuromorphic learning systems.

Abstract: In this paper we review several ways of realizing asynchronous Spike-Timing-Dependent-Plasticity (STDP) using memristors as synapses. Our focus is on how to use individual memristors to implement synaptic weight multiplications, in a way such that it is not necessary to (a) introduce global synchronization and (b) to separate memristor learning phases from memristor performing phases. In the approaches described, neurons fire spikes asynchronously when they wish and memristive synapses perform computation and learn at their own pace, as it happens in biological neural systems. We distinguish between two different memristor physics, depending on whether they respond to the original “moving wall” or to the “filament creation and annihilation” models. Independent of the memristor physics, we discuss two different types of STDP rules that can be implemented with memristors: either the pure timing-based rule that takes into account the arrival time of the spikes from the pre- and the post-synaptic neurons, or a hybrid rule that takes into account only the timing of pre-synaptic spikes and the membrane potential and other state variables of the post-synaptic neuron. We show how to implement these rules in cross-bar architectures that comprise massive arrays of memristors, and we discuss applications for artificial vision.