We describe a distributed position-based network protocol optimized for minimum energy consumption in mobile wireless networks that support peer-to-peer communications. Given any number of randomly deployed nodes over an area, we illustrate that a simple local optimization scheme executed at each node guarantees strong connectivity of the entire network and attains the global minimum energy solution for stationary networks. Due to its localized nature, this protocol proves to be self-reconfiguring and stays close to the minimum energy solution when applied to mobile networks. Simulation results are used to verify the performance of the protocol.

Minimum energy mobile wireless networks

We describe a distributed position-based network protocol optimized for minimum energy consumption in mobile wireless networks that support peer-to-peer communications. Given any number of randomly deployed nodes over an area, we show that a simple local optimization scheme executed at each node guarantees strong connectivity of the entire network and attains the global minimum energy solution for the stationary case. Due to its localized nature, this protocol proves to be self-reconfiguring and stays close to the minimum energy solution when applied to the case of mobile nodes. Our simulations verify its performance.

A monolithic 1.9-GHz, 198-mW, 0.6-/spl mu/m CMOS receiver which meets the specifications of the Digital Enhanced Cordless Telecommunications (DECT) standard is described. All of the RF, IF, and baseband receiver components, with the exception of the frequency synthesizers, have been integrated into a single chip solution. A description is given of a wide-band IF with double conversion architecture which eliminates the need for the discrete-component noise and IF filters in addition to facilitating the eventual integration of the frequency synthesizer blocks with on-chip VCO's. The prototype device utilizes a 3.3-V supply and includes a low noise amplifier, an image-rejection mixer, and two quadrature baseband signal paths each of which includes a second-order Sallen and Key anti-alias filter, an eighth-order switched-capacitor filter network followed by a 10-b pipelined analog-to-digital converter (ADC). The experimental device has a measured receiver reference sensitivity of -90 dBm, an input referred IP3 of -7 dBm, a P/sub -1 dB/ of -24 dBm, and an image-rejection ratio of -55 dBc across the DECT bands.

A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications

The concept of concurrent multiband low-noise-amplifiers (LNAs) is introduced. A systematic way to design concurrent multiband integrated LNAs in general is developed. Applications of concurrent multiband LNAs in concurrent multiband receivers together with receiver architecture are discussed. Experimental results of a dual-band LNA implemented in a 0.35-/spl mu/m CMOS technology as a demonstration of the concept and theory is presented.

/pdf/concurrent-multiband-low-noise-amplifiers-theory-design-and-1iy48rdapl.pdf

Concurrent multiband low-noise amplifiers-theory, design, and applications

I/Q signal processing is widely utilized in today's communication receivers However, all I/Q processing receiver structures, such as the low-IF receiver, face a common problem of matching the amplitudes and phases of the I and Q branches In practice, imbalances are unavoidable in the analog front-end, which results in finite and usually insufficient rejection of the image frequency band This causes the image signal to appear as interference on top of the desired signal We carry out general signal analysis of an imbalanced I/Q processing receiver and propose novel methods for I/Q imbalance compensation using baseband digital signal processing A simple structure for compensation is derived, based on a traditional adaptive interference canceller Improved image rejection can also be obtained by using more advanced blind source separation techniques Theoretical analysis of the performance of the proposed imbalance compensation structures is presented In addition, some simulation results are provided in order to further evaluate the performance of the proposed methods The results indicate that the I/Q imbalance can be effectively compensated during the normal operation of the receiver even in the rapidly changing case, as long as a linear system model for the imbalance is valid

Advanced methods for I/Q imbalance compensation in communication receivers

A physics-based effective gate resistance model representing the non-quasi-static (NQS) effect and the distributed gate electrode resistance is proposed for accurately predicting the RF performance of CMOS devices. The accuracy of the model is validated with 2D simulations and experimental data. In addition, the effect of the gate resistance on the device noise behavior has been studied with measured data. The result shows that an accurate gate resistance model is essential for the noise modeling.

/pdf/an-effective-gate-resistance-model-for-cmos-rf-and-noise-3kxuj1ileu.pdf

An effective gate resistance model for CMOS RF and noise modeling

A number of recent efforts have concentrated on highly-integrated radio receivers using a low-cost silicon process such as CMOS This prototype monolithic CMOS receiver combines RF and baseband functionality by taking the carrier signal at the LNA input and producing a 10 b digital baseband waveform A wide-band intermediate frequency double conversion (WBIFDC) architecture eliminates the need for external narrow-band IF filters

https://www.inst.bnl.gov/~poc/wireless/isscctalkf.pdf

A 1.9 GHz wide-band IF double conversion CMOS integrated receiver for cordless telephone applications

With the advent of submicron technologies, GHz RF circuits can now be realized in a standard CMOS process. A major barrier to the realization of robust commercial CMOS RF components is the lack of adequate models which accurately predict MOSFET device behavior at high frequencies. The conventional microwave table-lookup-based approach requires a large database obtained from numerous device measurements and computationally intense simulations for accurate results. This method becomes prohibitively complex when used to simulate highly integrated CMOS communication systems; hence, a compact model, valid for a broad range of bias conditions and operating frequencies is desirable. BSIM3v3 has been widely accepted as a standard CMOS model for low frequency applications. Recent work has demonstrated the capability of modeling CMOS devices at high frequencies by utilizing a complicated substrate resistance network and extensive modification to the BSIM3v3 source code. This paper first describes a unified device model realized with a lumped resistance network suitable for simulations of both RF and baseband analog circuits; then verifies the accuracy of the model to measured data on both device and circuit levels.

CMOS RF modeling for GHz communication IC's

Issues associated with the integration of transceiver components on to a single silicon substrate are discussed. In particular, recently proposed receiver and transmitter architectures for high integration are examined on the promise of providing multistandard capability. In addition, existing barriers to lower power transceiver operation are examined as well as some proposed directions for future integrated transceiver research and development.

Jia-Jiunn Ou

Papers

A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications

An effective gate resistance model for CMOS RF and noise modeling

A 1.9 GHz wide-band IF double conversion CMOS integrated receiver for cordless telephone applications

CMOS RF modeling for GHz communication IC's

Recent developments in high integration multi-standard CMOS transceivers for personal communication systems