Mobile devices demand low-power WiFi receivers for extended battery lifetime. This paper presents the design of an 11.6-mW receiver including baseband channel selection filtering that targets the IEEE802.11a standard. A 1-to-6 on-chip transformer serves as a low-noise amplifier with zero power dissipation and high linearity while providing ESD protection and differential outputs. The co-design of the transformer and the passive mixers leads to an efficient front end. Realized in 65-nm CMOS technology, the prototype exhibits a noise figure of 6 dB and a sensitivity of -66 dBm at a data rate of 54 Mb/s from 5 GHz to 5.9 GHz. A new analysis of fully-differential current-driven passive mixers is also presented to facilitate the design of the front end.

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A Low-Power CMOS Receiver for 5 GHz WLAN

A wideband and low phase noise quadrature local oscillation (LO) signal generator for multistandard cellular transceivers was proposed. Using the new LO-plan consisting of divide-by-6, divide-by-4, and divide-by-12 frequency dividers, the required frequency-tuning range (FTR) of a voltage-controlled oscillator (VCO) was reduced to 39%, which can be easily covered by a single LC -VCO. Due to the reduced FTR, the VCO can retain a high Q -factor and achieve low phase noise. The key building block of the new LO-plan is a quadrature divide-by-6 divider, capable of generating precise I / Q signals. To implement the quadrature divide-by-6 divider, we proposed a fully differential divide-by-3 divider with 50% duty cycle. Using the same idea, a fully differential divide-by-2 circuit was also proposed for divide-by-4 and divide-by-12 dividers. The proposed LO-generator was fabricated in a 40 nm CMOS process, and covered LO-frequencies of 0.56–2.92 GHz for multistandard cellular transceivers. The LO-generator occupied a small silicon area of $0.15\;\text{mm}^{2}$ and achieved an excellent phase noise performance of $- {141}.{02}\;\text{dBc}/\text{Hz}$ at a 1 MHz offset from a 709 MHz LO-frequency.

A 0.56–2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC -VCO for 2G–4G Multistandard Cellular Transceivers

The available ISM band from 57–65GHz has become attractive for high-speed wireless applications including mass data transfer, streaming high-definition video and even biomedical applications. While silicon based data transceivers at mm-wave frequencies have become increasingly mature in recent years [1,2,3], the primary focus of the circuit community remains on the design of mm-wave front-ends to achieve higher data rates through higher-order modulation and beamforming techniques. However, the sustainability of such mm-wave systems when integrated in a SoC has not been addressed in the context of die performance yield and device aging. This problem is especially challenging for the implementation of mm-wave SoC's in deep sub-micron technology due to its process & operating temperature variations and limited ft / fmax with respect to the operation frequency.

A low-overhead self-healing embedded system for ensuring high yield and long-term sustainability of 60GHz 4Gb/s radio-on-a-chip

A current-mode 60-GHz direct-conversion receiver, which can break performance tradeoffs among bandwidth, noise figure (NF), and linearity is designed and realized in 65-nm CMOS. The 60-GHz receiver employs the novel frequency-staggered series resonance common source (FSRCS) stage to extend RF bandwidth with superior noise performance. The receiver's current-mode operation offers excellent out-of-band blocker tolerance and linearity. With on-chip quadrature local oscillator generations, the fabricated receiver simultaneously achieves minimal NF of 3.8 dB, RF bandwidth of 7.5 GHz, output ${ P}_{1\ {\rm dB}}$ of 1 dBm, and maximum conversion gain of 36 dB. The receiver is capable of tolerating out-of-channel blocker up to $-$ 9 dBm at 3.5 GHz away. It occupies a silicon area of 1.3 ${\hbox{mm}}^{2}$ and draws 25.5 mA of current from a 1-V supply.

A Blocker-Tolerant Current Mode 60-GHz Receiver With 7.5-GHz Bandwidth and 3.8-dB Minimum NF in 65-nm CMOS

A current-mode mm-wave direct-conversion receiver breaking trade-offs among bandwidth, NF and linearity is designed and realized in 65nm CMOS. The 60GHz receiver employs novel Frequency-staggered Series Resonance Common Source (FSRCS) stage to extend RF bandwidth with superior noise performance. The receiver's current-mode operation offers excellent out-of-band blocker tolerance and linearity. With on-chip quadrature LO generations, the fabricated receiver simultaneously achieves minimal noise figure of 3.8dB, RF bandwidth of 7.5GHz, output P1dB of 1dBm, maximum conversion gain of 32dB, and IRR of -35dB. The receiver is capable of tolerating outof-channel blocker up to -9dBm at 3.5GHz away. It occupies silicon area of 1.3mm2 and draws 25.5mA from 1V supply.

A Current-Mode mm-Wave direct-conversion receiver with 7.5GHz Bandwidth, 3.8dB minimum noise-figure and +1dBm P 1dB, out linearity for high data rate communications

This paper presents the design and implementation of a compact and low power quadrature local oscillator (LO) for creating 13.3-20 GHz signal initially from a differentially tuned LC-VCO and then converting it to the desired 5-10 GHz with continuous frequency coverage. To accomplish such purpose, a 4-stage differential injection-locked ring oscillator (ILRO) is used subsequently to the latch-based divider to generate quadrature output phases without restricting 50% duty cycle from input signals as those of conventional divide-by-2 approaches. When implemented in a 65 nm general purpose CMOS IC technology, the integrated quadrature-phased LO consumes 22 mA of current at a 1 V supply and is able to exhibit the worst-case phase noise of -104 dBc/Hz at 1 MHz offset across the entire 5-10 GHz band for intended cognitive radio applications.

A Compact and Low Power 5–10 GHz Quadrature Local Oscillator for Cognitive Radio Applications

A direct conversion receiver which consists of low noise amplifier (LNA), mixer and programmable gain amplifier (PGA) for V-band (60GHz) applications is designed and realized in 65nm CMOS. A novel two-dimensional passive g m -enhancement technique is devised to boost the conversion gain and lower the Noise Figure (NF) with insignificant power overhead. An overall minimum SSB NF of 3.9dB and a maximum power conversion gain of 60dB have been validated from such fabricated receiver that occupies core silicon area of 0.2mm2 and draws 34mA from 1V supply.

A 60dB gain and 4dB noise figure CMOS V-band receiver based on two-dimensional passive G m -enhancement

This paper presents a local oscillator (LO) that converts oscillation frequencies of 13.3–20GHz from a single-LC-tank VCO to the intended 5–10GHz with continuous frequency coverage. A 4-stage differential injection-locked ring oscillator (ILRO) is used after the latch-based divider to produce quadrature output phases without requiring 50% duty cycle of input signals as those of conventional divide-by-2 approaches. When implemented in 65nm CMOS, the prototype LO consumes 22mA at 1V supply and is able to exhibit a worst-case phase noise of −102dBc/Hz at 1MHz offset across the entire 5–10GHz band for projected cognitive radio applications.

Jianhua Lu

Papers

A Compact and Low Power 5–10 GHz Quadrature Local Oscillator for Cognitive Radio Applications

A 60dB gain and 4dB noise figure CMOS V-band receiver based on two-dimensional passive G m -enhancement

A single-LC-tank 5–10 GHz quadrature local oscillator for cognitive radio applications