Jianhui Huang

Bio: Jianhui Huang is an academic researcher from Intel. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 7, co-authored 8 publications receiving 737 citations. Previous affiliations of Jianhui Huang include University of California, Berkeley.

Threshold voltage model for deep-submicrometer MOSFETs

Abstract: The threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep-submicrometer range has been investigated. Experimental data show that in the very-short-channel-length range, the previously reported exponential dependence on channel length and the linear dependence on drain voltage no longer hold true. A simple quasi-two-dimensional model is used, taking into account the effects of gate oxide thickness, source/drain junction depth, and channel doping, to describe the accelerated V/sub th/ on channel length due to their lower drain-substrate junction built-in potentials. LDD devices also show less V/sub th/ dependence on drain voltage because the LDD region reduces the effective drain voltage. Based on consideration of the short-channel effects, the minimum acceptable length is determined. >

A physical and scalable I-V model in BSIM3v3 for analog/digital circuit simulation

Abstract: A new physical and continuous BSIM (Berkeley Short-Channel IGFET Model) I-V model in BSIM3v3 is presented for circuit simulation. Including the major physical effects in state-of-the art MOS devices, the model describes current characteristics from subthreshold to strong inversion as well as from the linear to the saturation operating regions with a single I-V expression, and guarantees the continuities of I/sub ds/, conductances and their derivatives throughout all V/sub gs/, V/sub ds/, and T/sub bs/, bias conditions. Compared with the previous BSIM models, the improved model continuity enhances the convergence property of the circuit simulators. Furthermore, the model accuracy has also been enhanced by including the dependencies of geometry and bias of parasitic series resistances, narrow width, bulk charge, and DIBL effects. The new model has the extensive built-in dependencies of important dimensional and processing parameters (e.g., channel length, width, gate oxide thickness, junction depth, substrate doping concentration, etc.). It allows users to accurately describe the MOSFET characteristics over a wide range of channel lengths and widths for various technologies, and is attractive for statistical modeling. The model has been implemented in the circuit simulators such as Spectre, Hspice, SmartSpice, Spice3e2, and so on.

A MOSFET electron mobility model of wide temperature range (77 - 400 K) for IC simulation

Abstract: Based on the physics of scattering mechanisms of MOSFET inversion layer carriers at different temperatures and vertical electric fields, a new unified mobility model of wide temperature (77 - 400 K) and range is proposed for IC simulation. Measurement data taken in a wide range of temperatures and electric fields are compared with the simulation results of a MOSFET current model implementing this new mobility equation. Excellent agreement between the simulation and measurement data is found.

A robust physical and predictive model for deep-submicrometer MOS circuit simulation

Abstract: An efficient physical and predictive model (the Berkeley short-channel insulated-gate FET model, or BSIM3) for deep-submicrometer MOSFETs is presented with emphasis on both digital and analog applications. BSIM3 has extensive built-in dependences of important dimensional and processing parameters such as channel length, width, gate oxide thickness, junction depth, substrate doping concentration, and LDD (lightly doped drain) structures. The model is compact, and time-consuming functions are excluded. The ease of parameter extraction was a major consideration. The number of parameters is small (/spl sim/25), and every parameter has a physical meaning; the effects of parameters on output characteristics are very predictive. This feature of BSIM3 makes statistical study of the device fabrication process possible. BSIM3 has been implemented in SPICE3 and the divergence problem is also greatly improved.

Elementary scattering theory of the Si MOSFET

Abstract: A simple one-flux scattering theory of the silicon MOSFET is introduced. Current-voltage (I-V) characteristics are expressed in terms of scattering parameters rather than a mobility. For long-channel transistors, the results reduce to conventional drift-diffusion theory, but they also apply to devices in which the channel length is comparable to or even shorter than the mean-free-path. The results indicate that for very short channels the transconductance is limited by carrier injection from the source. The theory also indicates that evaluation of the drain current in short-channel MOSFETs is a near-equilibrium transport problem, even though the channel electric field is large in magnitude and varies rapidly in space.

Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads

Abstract: Dynamic voltage scaling (DVS) reduces the power consumption of processors when peak performance is unnecessary. However, the achievable power savings by DVS alone is becoming limited as leakage power increases. In this paper, we show how the simultaneous use of adaptive body biasing (ABB) and DVS can be used to reduce power in high-performance processors. Analytical models of the leakage current, dynamic power, and frequency as functions of supply voltage and body bias are derived and verified with SPICE simulation. We then show how to determine the correct trade-off between supply voltage and body bias for a given clock frequency and duration of operation. The usefulness of our approach is evaluated on real workloads obtained using real-time monitoring of processor utilization for four applications. The results demonstrate that application of simultaneous DVS and ABB results in an average energy reduction of 48% over DVS alone.

Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review

Abstract: This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.

Nanoscale CMOS

Abstract: This paper examines the apparent limits, possible extensions, and applications of CMOS technology in the nanometer regime. Starting from device scaling theory and current industry projections, we analyze the achievable performance and possible limits of CMOS technology from the point of view of device physics, device technology, and power consumption. Various possible extensions to the basic logic and memory devices are reviewed, with emphasis on novel devices that are structurally distinct front conventional bulk CMOS logic and memory devices. Possible applications of nanoscale CMOS are examined, with a view to better defining the likely capabilities of future microelectronic systems. This analysis covers both data processing applications and nondata processing applications such as RF and imaging. Finally, we speculate on the future of CMOS for the coming 15-20 years.

Scaling of stack effect and its application for leakage reduction

Abstract: Technology scaling demands a decrease in both V/sub dd/ and V/sub t/ to sustain historical delay reduction, while restraining active power dissipation. Scaling of V/sub t/ however leads to substantial increase in the sub-threshold leakage power and is expected to become a considerable constituent of the total dissipated power. It has been observed that the stacking of two off devices has smaller leakage current than one off device. In this paper we present a model that predicts the scaling nature of this leakage reduction effect. Device measurements are presented to prove the model's accuracy. Use of stack effect for leakage reduction and other implications of this effect are discussed.