Due to wider band gap of silicon carbide (SiC) compared to silicon (Si), MOSFET made in SiC has considerably lower drift region resistance, which is a significant resistive component in high-voltage power devices. With low on-state resistance and its inherently low switching loss, SiC MOSFETs can offer much improved efficiency and compact size for the converter compared to those using Si devices. In this paper, we report switching performance of a new 1700-V, 50-A SiC MOSFET designed and developed by Cree, Inc. Hard-switching losses of the SiC MOSFETs with different circuit parameters and operating conditions are measured and compared with the 1700-V Si BiMOSFET and 1700-V Si IGBT, using same test set-up. Based on switching and conduction losses, the operating boundary of output power and switching frequency of these devices are found out in a dc–dc boost converter and compared. The switching $dv/dts$ and $di/dts$ of SiC MOSFET are captured and discussed in the perspective of converter design. To validate the continuous operation, three dc–dc boost converters using these devices, are designed and tested at 10 kW of power with 1 kV of output voltage and 10 kHz of switching frequency. 1700-V SiC Schottky diode is used as the blocking diode in each case. Corresponding converter efficiencies are evaluated and the junction temperature of each device is estimated. To demonstrate high switching frequency operation, the SiC MOSFET is switched upto 150 kHz within permissible junction temperature rise. A switch combination of the 1700-V SiC MOSFET and 1700-V SiC Schottky diode connected in series is also evaluated for zero voltage switching turn-ON behavior and compared with those of bipolar Si devices. Results show substantial power loss saving with the use of SiC MOSFET.

High Switching Performance of 1700-V, 50-A SiC Power MOSFET Over Si IGBT/BiMOSFET for Advanced Power Conversion Applications

This paper addresses the influences of device and circuit mismatches on paralleling the silicon carbide (SiC) MOSFETs. Comprehensive theoretical analysis and experimental validation from paralleled discrete devices to paralleled dies in multichip power modules are first presented. Then, the influence of circuit mismatch on paralleling SiC MOSFETs is investigated and experimentally evaluated for the first time. It is found that the mismatch of the switching loop stray inductance can also lead to on-state current unbalance with inductive output current, in addition to the on-state resistance of the device. It further reveals that circuit mismatches and a current coupling among the paralleled dies exist in a SiC MOSFET multichip power module, which is critical for the transient current distribution in the power module. Thus, a power module layout with an auxiliary source connection is developed to reduce such a coupling effect. Finally, simulations and experimental tests are carried out to validate the analysis and effectiveness of the developed layout.

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Influences of Device and Circuit Mismatches on Paralleling Silicon Carbide MOSFETs

The double pulse test (DPT) is a widely accepted method to evaluate the dynamic behavior of power devices. Considering the high switching-speed capability of wide band-gap devices, the test results are very sensitive to the alignment of voltage and current (V-I) measurements. Also, because of the shoot-through current induced by Cdv/dt (i.e., cross-talk), the switching losses of the nonoperating switch device in a phase-leg must be considered in addition to the operating device. This paper summarizes the key issues of the DPT, including components and layout design, measurement considerations, grounding effects, and data processing. Additionally, a practical method is proposed for phase-leg switching loss evaluation by calculating the difference between the input energy supplied by a dc capacitor and the output energy stored in a load inductor. Based on a phase-leg power module built with 1200-V/50-A SiC MOSFETs, the test results show that this method can accurately evaluate the switching loss of both the upper and lower switches by detecting only one switching current and voltage, and it is immune to V-I timing misalignment errors.

Methodology for Wide Band-Gap Device Dynamic Characterization

SiC MOSFETs exhibit extremely fast switching characteristics, which are unfortunately accompanied by undesirable switching oscillations. In this paper, equivalent circuit models incorporating all parasitic elements are developed for the turn-ON and turn-OFF of a SiC MOSFET. Simple mathematical formulas are derived to provide the theoretical analysis of the switching oscillation phenomenon, and to guide the snubber or damping circuit design. Both circuit simulation and experimental measurement are carried out to validate these simple equivalent circuit models.

Modeling and Analysis of SiC MOSFET Switching Oscillations

Wide-bandgap (WBG) power semiconductor devices have become increasingly popular due to their superior characteristics compared to their Si counterparts. However, their fast switching speed and the ability to operate at high frequencies brought new challenges, among which the electromagnetic interference (EMI) is one of the major concerns. Many works investigated the structures of WBG power devices and their switching performance. In some cases, the conductive or radiated EMI was measured. However, the EMI-related topics, including their influence on noise sources, noise propagation paths, EMI reduction techniques, and EMC reliability issues, have not yet been systematically summarized for WBG devices. In this article, the literature on EMI research in power electronics systems with WBG devices is reviewed. Characteristics of WBG devices as EMI noise sources are reviewed. EMI propagation paths, near-field coupling, and radiated EMI are surveyed. EMI reduction techniques are categorized and reviewed. Specifically, the EMI-related reliability issues are discussed, and solutions and guidelines are presented.

A Survey of EMI Research in Power Electronics Systems With Wide-Bandgap Semiconductor Devices

This paper presents a comprehensive study on the influences of parasitic elements on the MOSFET switching performance. A circuit-level analytical model that takes MOSFET parasitic capacitances and inductances, circuit stray inductances, and reverse current of the freewheeling diode into consideration is given to evaluate the MOSFET switching characteristics. The equations derived for emulating MOSFET switching transients are assessed graphically, which, compared to results obtained merely from simulation or parametric study, can offer better insight into where the changes in switching performance lie when the parasitic elements are varied. The analysis has been successfully substantiated by the experimental results of a 400 V, 6 A test bench. A discussion on the physical meanings behind these parasitic effect phenomena is included. Knowledge about the effects of parasitic elements on the switching behavior serves as an important basis for the design guidelines of fast switching power converters.

Characterization and Experimental Assessment of the Effects of Parasitic Elements on the MOSFET Switching Performance

This paper derives a circuit-level analytical model for describing the mechanism of the spurious triggering pulse in the gate-source voltage of the synchronous MOSFET (SyncFET) in the synchronous buck converter. The model takes into account not only the parasitic capacitances and inductances of the control MOSFET (CtrlFET) and the SyncFET, but also the reverse recovery characteristics of the body diode of the SyncFET. An exhaustive investigation into the impact of all these factors on the spurious triggering pulse is conducted. The spurious triggering pulse can be attributed to two factors. The first one is the positive gate voltage caused by the displacement current through the gate-drain capacitance of the SyncFET, due to the increase in the drain-source voltage. The second one is the negative source voltage caused by the voltage drop across the source inductance of the SyncFET, due to the decrease in the drain current. It is discovered that the gate impedance of the SyncFET would exert different influence on the magnitude of the spurious triggering pulse, depending on the contributions of these two factors. Experimental results affirm that variation in the magnitude of the spurious triggering pulse with each parasitic element can be correctly inferred by the proposed model. Design guidelines for enhancing spurious turn-on immunity are advanced.

Impact of Parasitic Elements on the Spurious Triggering Pulse in Synchronous Buck Converter

With the increase in the switching speed and power level in the bridge-leg configuration, the spurious triggering pulse in the synchronous switch is prone to exceed the threshold voltage and cause spurious turn-on. Eliminating the spurious turn-on phenomenon plays an important role in preventing excessive switching loss, self-oscillation, and shoot-through in the bridge-leg configuration. A novel resistor-capacitor-diode ( RCD) level shifter is proposed to generate a negative gate voltage so that the spurious triggering pulse can be shifted below the threshold voltage, and thereby, the spurious turn-on can be avoided. The merits of the devised auxiliary circuit lie not merely in that it consists only of passive components and can easily be co-packaged with the existing gate driver, but also in that the negative voltage level is tunable and independent of the duty cycle of the converter. The effectiveness of this circuit has been verified by the experimental results. It is shown that when the spurious turn-on occurs in a bridge-leg configuration, the adoption of the proposed circuit can eliminate the spurious turn-on and reduce the turn-off switching loss by more than 40%.

A Novel RCD Level Shifter for Elimination of Spurious Turn-on in the Bridge-Leg Configuration

Limiting the spurious triggering pulse in the gate-source voltage of the lower MOSFET during the turn-on transition of the upper MOSFET is mandatory to prevent substantial switching loss and even shoot-through in the synchronous buck converter. This paper conducts an exhaustive investigation into the impact of the inherent parasitic elements on the spurious triggering pulse to facilitate a reliability-oriented design. An analytical model that considers the parasitic capacitances and inductances, reverse recovery characteristics of the body diode and the interaction between the upper and the lower MOSFETs is established to quantify this pulse. The spurious triggering pulse is found to stem from the induced increase in the gate voltage and the induced decrease in the source voltage. Variation in the magnitude of the spurious triggering pulse in regard to each parasitic element is identified accordingly. Experimental results of a practical synchronous buck converter affirm the theoretical analysis.

Impact of parasitic elements on the spurious triggering pulse in synchronous buck converter

This paper presents an investigation into the effects of the gate drive resistance on the losses of the MOSFET-snubberdiode (MSD) configuration commonly used in many power converters. An analytical loss model that takes the circuit stray inductances, MOSFET parasitic capacitances and inductances, and reverse current characteristic of the freewheeling diode into consideration is derived to describe the interactions among the MOSFET, snubber, and freewheeling diode during the switching transients. Two possible turn-ON switching situations, determined by the gate drive part and the power part, respectively, are distinguished in the analysis. It is then used to study the effects of the stray inductances, gate drive resistance and snubber on the switching behaviors, power loss distribution, and voltage stress on the MOSFET in the entire MSD configuration. A sequence of steps will be given to illustrate how an optimal combination of the gate drive resistance and snubber capacitance is determined, in order to minimize the overall loss of the MSD configuration for a maximum permissible voltage stress on the MOSFET. The loss model and method of determining the gate drive resistance and snubber capacitance are evaluated by comparing the theoretical predictions with the experimental results of a 400V, 6A test bench. The performances of the MSD configuration with different types of freewheeling diodes will be studied.

Jianjing Wang

Papers

Characterization and Experimental Assessment of the Effects of Parasitic Elements on the MOSFET Switching Performance

Impact of Parasitic Elements on the Spurious Triggering Pulse in Synchronous Buck Converter

A Novel RCD Level Shifter for Elimination of Spurious Turn-on in the Bridge-Leg Configuration

Impact of parasitic elements on the spurious triggering pulse in synchronous buck converter

An Investigation Into the Effects of the Gate Drive Resistance on the Losses of the MOSFET–Snubber–Diode Configuration