A process, voltage, and temperature (PVT)-stabilized dynamic amplification technique is reported for the pipelined-successive-approximation-register (SAR) analog-to-digital converter (ADC). A non-interleaved 12-b 330-MS/s pipelined-SAR ADC prototype employing such technique achieves 0.5- and 0.8-dB signal-to-noise plus distortion ratio (SNDR) variations for supply voltage varying from 1.25 to 1.35 V and temperature varying from −5 °C to 85 °C, respectively. The corresponding residue gain variations are 1.5% and 1.2% under the same conditions, respectively. Moreover, 2-b/cycle SAR architecture together with the attenuated passive residue transfer technique is employed to boost the prototype conversion throughput significantly. Noise analyses of the attenuated passive residue transfer process and of the PVT stabilization circuit are also furnished. At 330 MS/s, the 65-nm CMOS prototype achieves an SNDR of 63.5 dB and a Walden FoM of 15.4 fJ/conversion step for a near-Nyquist input.

A Non-Interleaved 12-b 330-MS/s Pipelined-SAR ADC With PVT-Stabilized Dynamic Amplifier Achieving Sub-1-dB SNDR Variation

This paper describes a single-channel, calibration-free Successive-Approximation-Register (SAR) ADC with a resolution of 10 bits at 240 MS/s. A DAC switching technique and an addition-only digital error correction technique based on the non-binary search are proposed to tackle the static and dynamic non-idealities attributed to capacitor mismatch and insufficient DAC settling. The conversion speed is enhanced, and the power and area of the DAC are also reduced by 40% as a result. In addition, a switching scheme lifting the input common mode of the comparator is proposed to further enhance the speed. Moreover, the comparator employs multiple feedback paths for an enhanced regeneration strength to alleviate the metastable problem. Occupying an active area of 0.003 mm $^{2}$ and dissipating 0.68 mW from 1 V supply at 240 MS/s in 28 nm CMOS, the proposed design achieves an SNDR of 57 dB with low-frequency inputs and 53 dB at the Nyquist input. This corresponds to a conversion efficiency of 4.8 fJ/c.-s. and 7.8 fJ/c.-s. respectively. The DAC switching technique improves the INL and DNL from +1.15/-1.01 LSB and +0.92/-0.28 LSB to within +0.55/-0.45 LSB and +0.45/-0.23 LSB, respectively. This ADC is at least 80% smaller and 32% more power efficient than reported state-of-the-art ADCs of similar resolutions and Nyquist bandwidths larger than 75 MHz.

A 0.003 mm $^{2}$ 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching

A two-time interleaved pipelined SAR ADC in 16-nm CMOS achieving 11.2-bit ENOB at 300 MS/s is presented. To cancel the signal-dependent voltage ripple on the reference node due to DAC switching, it employs a stabilization scheme based on the use of auxiliary DACs. The charge drawn from the reference becomes signal-independent, greatly reducing the requirements for the reference decoupling capacitance and/or buffers. The technique improves the linearity to levels better than 76-dB harmonic distortion. Power consumption is only 3.6 mW resulting in peak FoMs of 175.5 dB and 5.1 fJ/conv.step.

A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization

This brief presents a high-speed successive approximation register analog-to-digital converter (ADC) with nonbinary searching technique. By inserting redundancy in the first five decision steps, the digital-to-analog converter (DAC) settling errors can be tolerated and settling time can thus be reduced. In addition, split capacitor technology has also been adopted to further boost the conversion speed. With split switching method, no common mode voltage is needed in DAC reset phase and dynamic offset can be removed as well. Full adder-based encoder is employed to convert the raw 11-bit to 10-bit binary codes, showing less power penalty. The prototype ADC fabricated in 65-nm CMOS achieves 51.1 dB SNDR and 62.3 dB SFDR at 150-MS/s sampling rate. It consumes 1.4 mW, resulting in a Walden figure of merit of 31.8 fJ/conversion step.

A 1.4-mW 10-Bit 150-MS/s SAR ADC With Nonbinary Split Capacitive DAC in 65-nm CMOS

This paper presents a reference error calibration scheme for successive approximation register (SAR) analog-to-digital converters (ADCs) verified with two prototypes. Such a reference error often occurs in high-speed SAR ADCs due to the signal dependent fast switching transient, and leads to a large differential nonlinearity and missing codes, eventually degrading conversion accuracy. The calibration concept aims to differentiate the error outputs and correct them by simply performing a subtraction in the digital domain. It runs in the background with a little hardware overhead, and does not depend on the type of the input signal or reduce the dynamic range. Two prototypes were measured which are made up of different reference generation circuits. Design #1 has the reference voltage from off-chip and a 3-pF decoupling capacitor on-chip, while design #2 includes an on-chip reference buffer. Both designs were fabricated in 65-nm CMOS and achieve at least 9-dB improvement on signal-to-(Noise + Distortion) ratio (SNDR) after calibration. The total core area is around 0.012 mm2 for both chips and the Nyquist SNDR of designs #1 and #2 is 59.03 and 57.93 dB, respectively.

60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration

This paper analyzes the thermal and reference noises of two types of successive-approximation-register (SAR) analog-to-digital converters (ADCs): the time-interleaving (TI) and the partial-interleaving (PI) Pipelined. The thermal noise is investigated with accurate estimation by deriving closed-form expressions according to the noise equivalent models on different phases. Additionally, the design trade-off between power and noise for two ADC architectures is discussed in detail. On the other hand, the reference noise due to the large switching transient, which significantly degrades the conversion accuracy, is analyzed and verified through behavioral and circuit level simulations of two ADC architectures operating at 500 MS/s for 10-bit resolution. The simulated results show the supremacy of the PI Pipelined-SAR (PS) architecture over the TI-SAR because it exhibits less reference noise sensitivity.

Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs

This paper presents a 12b 180 MS/s 0.068 mm2 $2\times$ time-interleaved pipelined-SAR analog-to-digital conver-ter (ADC) with gain and offset calibrations fully embedded on-chip. The proposed binary-search gain calibration (BSGC) technique corrects the inter-stage gain error caused by the open-loop residue amplifier. The BSGC, fully integrated into the second-stage SAR ADC, contributes to a compact area. We improve the noise performance by implementing a merged-residue-DAC operation in the first-stage ADC. Also, we propose a dual-phase bootstrap technique to improve the sampling linearity in the partial interleaving architecture. The measurement results of the ADC prototype in 65 nm CMOS demonstrate the effectiveness of the proposed calibration through the enhancement of the signal to noise-and-distortion ratio from 51.5 to 60.9 dB at a Nyquist input, leading to a FoM@Nyq of 36.7 fJ/conversion-step.

A 12b 180MS/s 0.068mm 2 With Full-Calibration-Integrated Pipelined-SAR ADC

This paper presents a 12b 180 MS/s partial-interleaving Pipelined-SAR analog-to-digital converter (ADC). The 1st-stage is implemented with a 2b/cycle SAR ADC for high speed, where we propose a merged-residue-DAC technique to improve the noise performance. The capacitor pre-charging in conventional 2b/cycle operation wastes settling time and switching energy, while with this design approach the switching procedure is optimized to avoid the pre-charging for tri-level reference generation. The prototype ADC fabricated in 65nm CMOS achieves a SNDR of 63.8dB @DC input with 6mW power dissipation from a 1.2V supply, leading to a FoM @DC of 26.3 fJ/conv.-step.

A 12b 180MS/s 0.068mm 2 pipelined-SAR ADC with merged-residue DAC for noise reduction

This paper presents a 2.3 GS/s 12-way time-interleaved pipelined-SAR ADC achieving 1.1 GHz input bandwidth with 47.4 dB signal-to-noise distortion ratio (SNDR). Here, we propose a hierarchical interleaving with passively shared sub-sampling front-end to eliminate the timing skews, thus avoiding the timing calibration for design simplicity as well as better area and power efficiency. To provide a fast signal transfer with good power efficiency to the sub-ADCs, the power and bandwidth trades off by using the passive sharing or active buffers are analyzed according to our developed mathematic model. The analysis is based on two scenarios: noise and matching limited sampling. Moreover, we propose a boosting-capacitor-sharing technique to enhance the compactness of the time-interleaved bootstrapped sampling front-end, which is particularly critical when omitted the time calibration in this design. Measurement results on a 65 nm CMOS prototype operated at 2.3 GS/s and 1.2 V supply show 31 mW total power consumption with a SNDR of 47.4 dB @Nyquist leading to a FOM of 69 fJ/conv.step.

A 0.19 mm 2 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS

This paper proposes an Inter-Stage Gain Error (ISGE) calibration method devoted to correct the residue gain errors induced by the parasitic effects, non-ideal op-amp gain and capacitor mismatch, and also the mismatches for supply-derived reference voltages between two stages for Pipelined-SAR ADC. The calibration reuses the SAR ADC to estimate the overall inter-stage gain error and compensates it in the 2nd-stage DAC in 2 cycles, and it is implemented in a Pipelined-SAR which achieves 10b 470 MS/s in 65 nm CMOS with the FoM of 31.5 fJ/conv.-step by consuming only 6% of the total ADC area (0.049 mm2).

Jianyu Zhong

Papers

Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs

A 12b 180MS/s 0.068mm 2 With Full-Calibration-Integrated Pipelined-SAR ADC

A 12b 180MS/s 0.068mm 2 pipelined-SAR ADC with merged-residue DAC for noise reduction

A 0.19 mm 2 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS

Inter-Stage Gain Error self-calibration of a 31.5fJ 10b 470MS/S Pipelined-SAR ADC