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Jiaw-Ren Shih

Other affiliations: TSMC
Bio: Jiaw-Ren Shih is an academic researcher from National Tsing Hua University. The author has contributed to research in topics: Shallow trench isolation & Layer (electronics). The author has an hindex of 7, co-authored 15 publications receiving 175 citations. Previous affiliations of Jiaw-Ren Shih include TSMC.

Papers
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Patent
30 Sep 1999
TL;DR: In this paper, a new method is provided for the creation of a Shallow Trench Isolation region, where a layer of pad oxide and nitride are patterned and etched over the region where the STI is to be formed.
Abstract: A new method is provided for the creation of a Shallow Trench Isolation region. A layer of pad oxide is deposited on the surface of a substrate; a layer of nitride is deposited over the layer of pad oxide. The layers of pad oxide and nitride are patterned and etched over the region where the STI is to be formed, a trench is etched in the silicon for the STI region. A layer of TEOS, that serves as a buffer spacer oxide, is deposited over the surface of the layer of nitride thereby including the inside of the created trench. The layer of TEOS is etched removing the TEOS from the surface of the nitride and from the bottom of the trench but leaving a layer of TEOS in place along the sidewalls of the trench. The bottom of the trench is next etched after which the TEOS spacer buffer is removed from the sidewalls of the trench. The sidewalls of the trench now have a non-linear profile. A layer of TEOS is deposited and polished leaving the trench filled with TEOS and at the same time removing the nitride from the surface of the pad oxide. N-well and P-well implants are performed after which N+ and P+ implants are performed around the periphery of the STI trench.

86 citations

Patent
14 Oct 1999
TL;DR: In this paper, a plasma damage protection cell using floating N/P/N and P/N/P structure is presented. But the method to form the same is not described.
Abstract: A plasma damage protection cell using floating N/P/N and P/N/P structure, and a method to form the same are disclosed. Floating structures of the protection cell and the floating gates for the MOS devices are formed simultaneously on a semiconductor substrate having shallow trench isolation. The floating structures are implanted separately to form the N/P/N and P/N/P bipolar base, emitter and collector regions while the source/drain of the respective NMOS and PMOS devices are implanted with appropriate sequencing. The floating structures are connected to the substrate with appropriate polarity to provide protection at low leakage current levels and with tunable punch-through voltages.

20 citations

Patent
02 Jul 1999
TL;DR: In this paper, a gate pocket implantation and post-processing sequence that allows for the creation of a deep and narrow pocket implant without affecting gate threshold voltage and the integrity of the gate oxide layer is presented.
Abstract: The invention provides a gate pocket implantation and post-processing sequence that allows for the creation of a deep and narrow pocket implant without affecting gate threshold voltage and the integrity of the gate oxide layer.

15 citations

Patent
07 Feb 2000
TL;DR: In this paper, a method for incorporating an ion implanted channel stop layer under field isolation for a twin-well CMOS process is described in which the layer is placed directly under the completed field isolation by a blanket boron ion implant over the whole wafer.
Abstract: A method for incorporating an ion implanted channel stop layer under field isolation for a twin-well CMOS process is described in which the layer is placed directly under the completed field isolation by a blanket boron ion implant over the whole wafer. The channel stop implant follows planarization of the field oxide and is thereby essentially at the same depth in both field and active regions. Subsequently implanted p- and n-wells are formed deeper than the channel stop layer, the n-well implant being of a sufficiently higher dose to over compensate the channel stop layer, thereby removing it's effect from the n-well. A portion of the channel stop implant under the field oxide adjacent the p-well provides effective anti-punchthrough protection with only a small increase in junction capacitance. The method is shown for, and is particularly effective in, processes utilizing shallow trench isolation.

15 citations

Journal ArticleDOI
TL;DR: In this paper, a p-channel nitride-based one-time programmable (OTP) memory was developed for advanced-logic nonvolatile memory (NVM) applications.
Abstract: A new p-channel nitride-based one-time programmable (OTP) memory was developed for advanced-logic nonvolatile-memory (NVM) applications. A 0.296-mum2/bit (~35 F2) OTP cell, i.e., 0.592 mum2/cell, with a self-aligned nitride storage node was fabricated using standard 90-nm CMOS processes and is fully independent of gate oxide for high scalability. Additionally, the ultrahigh-density OTP cell exhibits excellent retention, immunity against disturbance, and a wide on/off window under the band-to-band hot electron programming. In summary, the new p-channel OTP cell is a very promising solution for use in high-density logic NVM applications beyond the 90-nm technology node.

10 citations


Cited by
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Patent
11 May 2007
TL;DR: In this article, a method for fabricating a semiconductor device, in which a lifting phenomenon can be prevented from occurring in forming an amorphous carbon film on an etched layer having tensile stress, was proposed.
Abstract: A method for fabricating a semiconductor device, in which a lifting phenomenon can be prevented from occurring in forming an amorphous carbon film on an etched layer having tensile stress. According to the invention, since a compression stress on the etched layer or the amorphous carbon film can be reduced or a compression stress film is formed between the etched layer or the amorphous carbon film to prevent a lifting phenomenon from occurring and thus another pattern can be formed to fabricate a highly integrated semiconductor device.

212 citations

Patent
16 Aug 2006
TL;DR: In this paper, a dry etching method and apparatus for silicon nitride and silicon dioxide is described, where a workpiece is exposed to a plasma containing at least one of sulfur hexafluoride and nitrogen trifluorides and ammonia to selectively remove the silicon nitrid in relation to the silicon dioxide.
Abstract: A dry etching method and apparatus are described. A workpiece supports silicon nitride and silicon dioxide. The workpiece is exposed to a plasma containing at least one of sulfur hexafluoride and nitrogen trifluoride and ammonia to selectively remove the silicon nitride in relation to the silicon dioxide. In one feature, the plasma contains sulfur hexafluoride and ammonia. In another feature, the plasma contains nitrogen trifluoride and ammonia.

140 citations

Patent
05 Sep 2008
TL;DR: In this paper, the conductive structure is formed over at least part of the planar portion and not over the protrusion portion of the via structure of a semiconductor device.
Abstract: A semiconductor device includes a via structure and a conductive structure. The via structure has a surface with a planar portion and a protrusion portion. The conductive structure is formed over at least part of the planar portion and not over at least part of the protrusion portion of the via structure. For example, the conductive structure is formed only onto the planar portion and not onto any of the protrusion portion for forming high quality connection between the conductive structure and the via structure.

95 citations

Patent
12 Sep 2000
TL;DR: In this article, a method of fabricating a SOI semiconductor device with an implanted ground plane in the silicon substrate to increase the doping concentration underneath the channel region for suppressing short channel effects (SCEs) such as drain-induced barrier lowering (DIBL).
Abstract: A method of fabricating a SOI semiconductor device with an implanted ground plane in the silicon substrate to increase the doping concentration underneath the channel region for suppressing short-channel effects (SCEs) such as drain-induced barrier lowering (DIBL). For a N-channel MOSFET, the implanted ground plane is P+ type such that if a P-type underlying substrate is used, the ground plane is automatically connected to ground potential (the substrate potential). For a SOI-type CMOS semiconductor device with two spaced-apart implanted ground planes each self-aligned to be underneath a corresponding channel region of the CMOS, two SOI-type MOSFET semiconductor devices of opposite conductivity types are formed on a same semiconductor substrate. The increase in doping concentration underneath the channel region prevents the electric field lines from the gate from terminating under the channel region; instead, the electric field lines terminate in the ground plane, thereby suppressing the short-channel effects and the off-state leakage current of the MOSFETs.

77 citations

Patent
Jack A. Mandelman1, William R. Tonti1
22 Oct 2007
TL;DR: In this paper, a latch-up resistant device is constructed on a hybrid substrate, which is characterized by first and second semiconductor regions that are formed on a bulk semiconductor region.
Abstract: Device structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes latch-up resistant devices formed on a hybrid substrate. The hybrid substrate is characterized by first and second semiconductor regions that are formed on a bulk semiconductor region. The second semiconductor region is separated from the bulk semiconductor region by an insulating layer. The first semiconductor region is separated from the bulk semiconductor region by a conductive region of an opposite conductivity type from the bulk semiconductor region. The buried conductive region thereby the susceptibility of devices built using the first semiconductor region to latch-up.

75 citations