Jietao Diao

Bio: Jietao Diao is an academic researcher from National University of Defense Technology. The author has contributed to research in topics: Finite impulse response & Distortion. The author has an hindex of 2, co-authored 8 publications receiving 16 citations.

Hardware-Efficient Parallel FIR Filter Structure Based on Modified Cook-Toom Algorithm

Abstract: The Cook-Toom algorithm is widely used in short-length linear convolution, which is the building block of large points convolution algorithms. This paper proposes improved parallel finite impulse response (FIR) filter structures for linear-phase FIR filter, which is based on the Cook-Toom algorithm. In the proposed structures, Cook-Toom algorithm is used to reduce the number of sub-filters, and the symmetric properties of the linear-phase FIR filter’s coefficients is used to further reduce the number of multipliers in sub-filters. Compared with the reported FFA and ISCA parallel FIR filter structures, the proposed method can substantially reduce the computational complexity. Specifically, for a 8-parallel 144-tap filter, the proposed design saves 18 multipliers (5%), 45 adders (7.9%) compared with the structure based on Winograd convolution algorithm [7].

Minimax design and order estimation of FIR filters for extending the bandwidth of ADCs

Abstract: The bandwidth of the sampling systems, especially for time-interleaved analog-to-digital converters, needs to be extended along with the rapid increase of the sampling rate. A digitally assisted technique becomes a feasible approach to extend the analog bandwidth, as it is impractical to implement the extension in analog circuits. This paper derives accurate order estimation formulas for the bandwidth extension filter, which is designed in the minimax sense with the ripple constraints as the design criteria. The derived filter order estimation is significant in evaluating the computational complexity from the viewpoint of the top-level system design. Moreover, with the proposed order estimates, one can conveniently obtain the minimal order that satisfies the given ripple constraints, which contributes to reducing the design time. Both the performance of the extension filter and its order estimation are illustrated and demonstrated through simulation examples.

Bandwidth-efficient calibration method for nonlinear errors in M-channel time-interleaved ADCs

Abstract: In order to enhance the effective resolution of time-interleaved analog-to-digital converters (TI-ADCs), both linear and nonlinear channel mismatches should be carefully calibrated. This paper concentrates on a bandwidth-efficient background calibration method for nonlinear errors in M-channel TI-ADCs. It utilizes the least-mean square algorithm as well as a certain degree of oversampling to achieve adaptive mismatch tracking. The calibration performance and computational complexity are investigated and evaluated through behavioral-level simulations. Furthermore, a calibration strategy for narrow-band input signals is proposed and verified as an improvement of the basic calibration structure for such signals.

Multi-chain time interval measurement method utilizing the dedicated carry chain of FPGA

Abstract: In this paper, we propose a high accuracy multi-chain time interval measurement (TIM) technique by employing the dedicated carry chain of FPGA. According to the principle of delay chain time to digital converter (TDC), the proposed method is realized by connecting the selectors inside the slices. The resolution of the delay chain method is limited by the time delay of one delay unit. To break through the resolution bottleneck of the delay chain approach, a TIM structure is adopted by utilizing the dedicated carry chain of FPGA. To verify the proposed method, we implement a multi-chain TIM circuit which consists of 16 chains in the Kintex-7 filed-programmable-gate arrays (FPGA). The post-route simulation results show that the bine size can be increased to 1.67ps and the RMS is enhanced to 3.99ps without bringing extra dead time. In addition, the proposed method is able to make full use of the delay unit, which reduces the hardware cost of the circuit by nearly 35% compared to the previous method.

A Pre-Compensation Method for Digital-to-Analog Converter Using Minimax-Designed FIR Filters

Abstract: The output frequency response for most DACs rolls off according to the sin(x)/x frequency-response envelope [1]. This paper derives a FIR filter which is designed in the minimax sense with the ripple constraints as the design criteria for the frequency response compensation of DACs. The filter order estimation function under the criterion gives a detailed filter design configuration method, which can effectively shorten the design time and provide an accurate resource configuration reference for the top-level system design [2]. The simulation example verifies the advantages of the compensation filter in minimax sense and shows the performance of the compensation filter and the accuracy of the order estimation function.

Recent Developments and Challenges in FPGA-Based Time-to-Digital Converters

Abstract: Over the past few years, the gap between field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) performance levels has been narrowed due to the constant development of FPGA technology. The high performance, together with the lower development costs and a shorter time to market, turns FPGA-based platforms attractive for a huge range of applications, among them time-to-digital converters (TDCs). It is, therefore, important to analyze the evolution of FPGA-based TDCs to better understand where the research efforts should be focused in the near future. This article presents and discusses the improvements on the FPGA-based TDC research, aiming to be a starting point for new studies on this field, with some guidelines for future research. A state-of-the-art literature review on the FPGA-based TDC is presented, aiming to categorize and discuss the existing architectures. This discussion addresses architectures’ characteristics, limitations, and areas of application.

An efficient blind calibration method for nonlinearity mis-matches in M-channel TIADCs

Abstract: As gain, offset, and timing mismatches, nonlinearity mismatches also contribute to spurious components which deteriorate TIADC’s performance. This paper proposes an efficient blind calibration method for nonlinearity mismatches in M-channel TIADCs. A modified model for nonlinearity mismatches is established by exploiting binary Hadamard transform (BHT) and differentiator. The calibration is composed of two stages— mismatches compensation and coefficients identification. The principle of mismatches compensation is to reconstruct estimations of the mismatchesinduced spurious components and subtract them from the original TIADC’s output. The coefficients identification is performed based on filtered-x least mean square (FxLMS) algorithm. By using improved model and calibration algorithm, the proposed method consumes less computational resource according to the complexity comparison. To tackle the 4-order nonlinearity mismatches in an 16-channel TIADC, the proposed method consumes 23% fewer multipliers than the previous work. Simulation results reveal that both effective resolution and dynamic range improve a lot after calibration.

A 10bit 120MSample/s Time-Interleaved Analog-to-Digital Converter with Digital Background Calibration

Abstract: Digital calibration using adaptive signal processing corrects offset mismatch, gain mismatch, and sample-time error between time-interleaved channels in a 10b 120MSample/s pipelined ADC. With background calibration, peak SNDR is 56.8dB and power dissipation is 234mW from 3.3V. Active area is 12.5mm/sup 2/ in 0.35/spl mu/m CMOS.

Calibration for Sample-And-Hold Mismatches in M-Channel TIADCs Based on Statistics

Abstract: Time-interleaved analog-to-digital converter (TIADC) is a good option for high sampling rate applications. However, the inevitable sample-and-hold (S/H) mismatches between channels incur undesirable error and then affect the TIADC’s dynamic performance. Several calibration methods have been proposed for S/H mismatches which either need training signals or have less extensive applicability for different input signals and different numbers of channels. This paper proposes a statistics-based calibration algorithm for S/H mismatches in M-channel TIADCs. Initially, the mismatch coefficients are identified by eliminating the statistical differences between channels. Subsequently, the mismatch-induced error is approximated by employing variable multipliers and differentiators in several Richardson iterations. Finally, the error is subtracted from the original output signal to approximate the expected signal. Simulation results illustrate the effectiveness of the proposed method, the selection of key parameters and the advantage to other methods.

Frequency Response Compensation with DSP

Abstract: This chapter contains sections titled: Filter Table Run-Time Filter Design Calibration Tables FIR Versus IIR Filters Linear Phase FIR Filters Sampling and Signal Frequency Filter Design MATLAB Simulation Implementation in C Extensions Calibration Tables References ]]>