Jiren Yuan

Bio: Jiren Yuan is an academic researcher from Lund University. The author has contributed to research in topics: CMOS & Interpolation. The author has an hindex of 20, co-authored 82 publications receiving 2127 citations. Previous affiliations of Jiren Yuan include Linköping University.

High-speed CMOS circuit technique

Abstract: It is shown that clock frequencies in excess of 200 MHz are feasible in a 3- mu m CMOS process. This performance can be obtained by means of clocking strategy, device sizing, and logic style selection. A precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used. Device sizing with the help of an optimizing program improves circuit speed by a factor of 1.5-1.8. The logic depth is minimized to one instead of two or more, and pipeline structures are used wherever possible. Experimental results for several circuits which work at clock frequencies of 200-230 MHz are presented. SPICE simulation shows that some circuits could work up to 400-500 MHz. >

New single-clock CMOS latches and flipflops with improved speed and power savings

Abstract: New dynamic, semistatic, and fully static single-clock CMOS latches and flipflops are proposed. By removing the speed and power bottlenecks of the original true-single-phase clocking (TSPC) and the existing differential latches and flipflops, both delays and power consumptions are considerably reduced. For the nondifferential dynamic, the differential dynamic, the semistatic, and the fully static flipflops, the best reduction factors are 1.3, 2.1, 2.2, and 2.4 for delays and 1.9, 3.5, 3.4, and 6.5 for power-delay products with an average activity ratio (0.25), respectively. The total and the clocked transistor numbers are decreased. In the new differential flipflops, clock loads are minimized and logic-related transistors are purely n-type in both n- and p-latches, giving additional speed advantage to this kind of CMOS circuits.

Double-edge-triggered D-flip-flops for high-speed CMOS circuits

Abstract: Two circuits are proposed for double edge-triggered D flip-flops (DETDFFs). A DETDFF responds to both edges of the clock pulse. As compared with positive or negative edge-triggered flip-flops, a DETDFF has advantages in terms of power dissipation and speed. Delay figures for these circuits are measured by simulation. It is shown that these circuits are faster and have lower transistor counts than previously reported circuits. It is shown that these flip-flops can be used at 320-400-MHz clock frequency in a 2- mu m technology. >

A 10-bit 5-MS/s successive approximation ADC cell used in a 70-MS/s ADC array in 1.2-/spl mu/m CMOS

Abstract: A 10-bit 5-MS/s successive approximation ADC cell and a 70-MS/s parallel ADC array based on this cell, designed and fabricated in a 1.2-/spl mu/m CMOS process, are presented. The ADC cell was designed to have an input bandwidth of more than 35 MHz and a sampling time of 14 nS at a clock rate of 70 MHz. The parallel ADC array consists of 14 such cells which are timed in one clock cycle skew successively in order to obtain digitized data every clock cycle. A two-step principle based on unsymmetrical dual-capacitor charge-redistribution-coupling has been used. With the help of a reset function, the comparator presents a fast response to the successive comparison. Each successive approximation ADC cell occupies an area of 0.6 mm/sup 2/ and the core of the parallel ADC array occupies an area of 2.7/spl times/3.3 mm/sup 2/. The power consumptions for the cell and the parallel ADC array are 18 mW and 267 mW respectively. >

Performance analysis of general charge sampling

Abstract: This brief focuses on the performance analysis of general charge-sampling circuits for signal capture. The theoretical analysis in the brief can be applied not only for weak signal capture, but also for the normal signal sampling. Based on a general charge-sampling model, the transfer function, the noise performance, and the clock jitter tolerance are analyzed and compared to conventional voltage sampling. The results provide a theoretical basis for charge-sampling circuit design.

Minimizing power consumption in digital CMOS circuits

Abstract: An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design. This optimization includes the technology used to implement the digital circuits, the circuit style and topology, the architecture for implementing the circuits and at the highest level the algorithms that are being implemented. The most important technology consideration is the threshold voltage and its control which allows the reduction of supply voltage without significant impact on logic speed. Even further supply reductions can be made by the use of an architecture-based voltage scaling strategy, which uses parallelism and pipelining, to tradeoff silicon area and power reduction. Since energy is only consumed when capacitance is being switched power can be reduced by minimizing this capacitance through operation reduction choice of number representation, exploitation of signal correlations, resynchronization to minimize glitching, logic design, circuit design, and physical design. The low-power techniques that are presented have been applied to the design of a chipset for a portable multimedia terminal that supports pen input, speech I/O and full-motion video. The entire chipset that performs protocol conversion, synchronization, error correction, packetization, buffering, video decompression and D/A conversion operates from a 1.1 V supply and consumes less than 5 mW. >

Low-power logic styles: CMOS versus pass-transistor logic

Abstract: Recently reported logic style comparisons based on full-adder circuits claimed complementary pass-transistor logic (CPL) to be much more power-efficient than complementary CMOS. However, new comparisons performed on more efficient CMOS circuit realizations and a wider range of different logic cells, as well as the use of realistic circuit arrangements demonstrate CMOS to be superior to CPL in most cases with respect to speed, area, power dissipation, and power-delay products. An implemented 32-b adder using complementary CMOS has a power-delay product of less than half that of the CPL version. Robustness with respect to voltage scaling and transistor sizing, as well as generality and ease-of-use, are additional advantages of CMOS logic gates, especially when cell-based design and logic synthesis are targeted. This paper shows that complementary CMOS is the logic style of choice for the implementation of arbitrary combinational circuits if low voltage, low power, and small power-delay products are of concern.

High-speed CMOS circuit technique

Abstract: It is shown that clock frequencies in excess of 200 MHz are feasible in a 3- mu m CMOS process. This performance can be obtained by means of clocking strategy, device sizing, and logic style selection. A precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used. Device sizing with the help of an optimizing program improves circuit speed by a factor of 1.5-1.8. The logic depth is minimized to one instead of two or more, and pipeline structures are used wherever possible. Experimental results for several circuits which work at clock frequencies of 200-230 MHz are presented. SPICE simulation shows that some circuits could work up to 400-500 MHz. >

Self-powered signal processing using vibration-based power generation

Abstract: Low power design trends raise the possibility of using ambient energy to power future digital systems. A chip has been designed and tested to demonstrate the feasibility of operating a digital system from power generated by vibrations in its environment. A moving coil electromagnetic transducer was used as a power generator. Calculations show that power on the order of 400 /spl mu/W can be generated. The test chip integrates an ultra-low power controller to regulate the generator voltage using delay feedback techniques, and a low power subband filter DSP load circuit. Tests verify 500 kHz self-powered operation of the subband filter, a level of performance suitable for sensor applications. The entire system, including the DSP load, consumes 18 /spl mu/W of power. The chip is implemented in a standard 0.8 /spl mu/m CMOS process. A single generator excitation produced 23 ms of valid DSP operation at a 500 kHz clock frequency, corresponding to 11,700 cycles.

Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems

Abstract: In this paper, we propose a set of rules for consistent estimation of the real performance and power features of the flip-flop and master-slave latch structures. A new simulation and optimization approach is presented, targeting both high-performance and power budget issues. The analysis approach reveals the sources of performance and power-consumption bottlenecks in different design styles. Certain misleading parameters have been properly modified and weighted to reflect the real properties of the compared structures. Furthermore, the results of the comparison of representative master-slave latches and flip-flops illustrate the advantages of our approach and the suitability of different design styles for high-performance and low-power applications.