J
João Canas Ferreira
Researcher at University of Porto
Publications - 95
Citations - 715
João Canas Ferreira is an academic researcher from University of Porto. The author has contributed to research in topics: Control reconfiguration & Field-programmable gate array. The author has an hindex of 13, co-authored 92 publications receiving 626 citations. Previous affiliations of João Canas Ferreira include Faculdade de Engenharia da Universidade do Porto.
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Journal ArticleDOI
Assessment of Eutrophication in Estuaries: Pressure–State–Response and Nitrogen Source Apportionment
TL;DR: These results suggest that Northeastern estuaries would likely benefit most from improved sewage treatment, where as the Mid and South Atlantic systems would benefitmost from agricultural runoff reductions.
Proceedings ArticleDOI
An FPGA implementation of a long short-term memory neural network
TL;DR: This work proposes a hardware architecture for a Long Short-Term Memory (LSTM) Neural Network, aiming to outperform software implementations, by exploiting its inherent parallelism, and synthesizes the network for various sizes and platforms.
Journal ArticleDOI
Support for partial run-time reconfiguration of platform FPGAs
TL;DR: The paper presents an approach inspired by the traditional software development: partial configurations are produced by assembling components from a previously created library, thus enabling the embedded application developer to produce the configuration data required for run-time modifications with less effort than is needed with the conventional design flow.
Proceedings ArticleDOI
Control and observation of analog nodes in mixed-signal boards
TL;DR: The paper presents a test support IC controlled by an IEEE1149.1 interface, capable of providing access to analog nodes in mixed-signal boards, and the proposed architecture (ABSINT - Analog to Boundary Scan Interface) is described and relevant implementation issues are discussed.
Journal ArticleDOI
Parallel Implementation on FPGA of Support Vector Machines Using Stochastic Gradient Descent
TL;DR: This work describes an implementation in hardware, using FPGA, of a fully parallel SVM using Stochastic Gradient Descent, and shows that the proposed architecture is a viable solution for highly demanding problems such as those present in big data analysis.