J
Joaquín Alvarado
Researcher at Benemérita Universidad Autónoma de Puebla
Publications - 54
Citations - 448
Joaquín Alvarado is an academic researcher from Benemérita Universidad Autónoma de Puebla. The author has contributed to research in topics: MOSFET & Transistor. The author has an hindex of 10, co-authored 51 publications receiving 390 citations. Previous affiliations of Joaquín Alvarado include National Autonomous University of Mexico & CINVESTAV.
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Computer-telephony integration that uses features of an automatic call distribution system
Joaquín Alvarado,Didina Burok,Andrew D. Flockhart,Eugene P. Mathews,Peter J. Matteo,Christopher Moss,Robert Daniel Nalbone +6 more
TL;DR: In this paper, a computer-telephony integrated (CTI) contact center, a CTI adjunct enqueues contacts in contact queues (184), but also causes contacts that are calls (168) to be enqueued as ACD calls in ACD call queues (120), whereby the ACD system and its management information system (MIS 110) provide ACD features to the calls.
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Implementation of the symmetric doped double-gate MOSFET model in Verilog-A for circuit simulation
TL;DR: In this paper, a model for symmetric double-gate MOSFETs (SDDGM) was developed for the first time, considering the doping concentration in the Si film in the complete range from 1×1014 to 3×1018 cm-3.
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Parasitic Gate Capacitance Model for Triple-Gate FinFETs
Silvestre Salas Rodriguez,Julio C. Tinoco,A. G. Martinez-Lopez,Joaquín Alvarado,Jean-Pierre Raskin +4 more
TL;DR: In this article, a semianalytical extrinsic gate capacitance model for silicon-on-insulator triple-gate FinFET, based on 3D numerical simulations, is presented.
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Impact of Extrinsic Capacitances on FinFET RF Performance
Julio C. Tinoco,Silvestre Salas Rodriguez,A. G. Martinez-Lopez,Joaquín Alvarado,Jean-Pierre Raskin +4 more
TL;DR: In this paper, the impact of the extrinsic gate capacitances on the RF behavior of FinFETs was analyzed based on measurements and 3-D numerical simulations, and it was shown that the reduction of the fin spacing, the modification of fin geometrical aspect ratio (height/width) as well as the optimization of fin spacing-fin Source/Drain extension ratio can significantly improve the finFET RF performance.
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Compact model for single event transients and total dose effects at high temperatures for partially depleted SOI MOSFETs
TL;DR: Well-known high tolerance of SOI circuits to a single event effects is demonstrated to be degraded with the total dose increase (appearing as a positive charge buildup), which is further enhanced at higher temperatures.