Silicon Photonics technology is rapidly maturing as a platform for larger-scale photonic circuits. As a result, the associated design methodologies are also evolving from componentoriented design to a more circuit-oriented design flow, that makes abstraction from the very detailed geometry and enables design on a larger scale. In this paper, we review the state of this emerging photonic circuit design flow and its synergies with electronic design automation (EDA). We cover the design flow from schematic capture, circuit simulation, layout and verification. We discuss the similarities and the differences between photonic and electronic design, and the challenges and opportunities that present themselves in the new photonic design landscape, such as variability analysis, photonic-electronic co-simulation and compact model definition. Silicon Photonics Circuit Design: Methods, Tools and

https://www.onlinelibrary.wiley.com/doi/epdf/10.1002/lpor.201700237

Silicon Photonics Circuit Design: Methods, Tools and Challenges

Cadence Design Systems Inc.

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Vlsi Physical Design From Graph Partitioning To Timing Closure

Handbook of Approximation: Algorithms and Metaheuristics

Spin–orbit torque (SOT) is an emerging technology that enables the efficient manipulation of spintronic devices. The initial processes of interest in SOTs involved electric fields, spin–orbit coupling, conduction electron spins, and magnetization. More recently, interest has grown to include a variety of other processes that include phonons, magnons, or heat. Over the past decade, many materials have been explored to achieve a larger SOT efficiency. Recently, holistic design to maximize the performance of SOT devices has extended material research from a nonmagnetic layer to a magnetic layer. The rapid development of SOT has spurred a variety of SOT-based applications. In this article, we first review the theories of SOTs by introducing the various mechanisms thought to generate or control SOTs, such as the spin Hall effect, the Rashba-Edelstein effect, the orbital Hall effect, thermal gradients, magnons, and strain effects. Then, we discuss the materials that enable these effects, including metals, metallic alloys, topological insulators, 2-D materials, and complex oxides. We also discuss the important roles in SOT devices of different types of magnetic layers, such as magnetic insulators, antiferromagnets, and ferrimagnets. Afterward, we discuss device applications utilizing SOTs. We discuss and compare three- and two-terminal SOT-magnetoresistive random access memories (MRAMs); we mention various schemes to eliminate the need for an external field. We provide technological application considerations for SOT-MRAM and give perspectives on SOT-based neuromorphic devices and circuits. In addition to SOT-MRAM, we present SOT-based spintronic terahertz generators, nano-oscillators, and domain-wall and skyrmion racetrack memories. This article aims to achieve a comprehensive review of SOT theory, materials, and applications, guiding future SOT development in both the academic and industrial sectors.

/pdf/roadmap-of-spin-orbit-torques-5gdnrw07hi.pdf

Roadmap of Spin–Orbit Torques

Layout camouflaging can protect the intellectual property of modern circuits. Most prior art, however, incurs excessive layout overheads and necessitates customization of active-device manufacturing processes, i.e., the front-end-of-line (FEOL). As a result, camouflaging has typically been applied selectively, which can ultimately undermine its resilience. Here, we propose a low-cost and generic scheme—full-chip camouflaging can be finally realized without reservations. Our scheme is based on obfuscating the interconnects, i.e., the back-end-of-line (BEOL), through design-time handling for real and dummy wires and vias. To that end, we implement custom, BEOL-centric obfuscation cells, and develop a CAD flow using industrial tools. Our scheme can be applied to any design and technology node without FEOL-level modifications. Considering its BEOL-centric nature, we advocate applying our scheme in conjunction with split manufacturing, to furthermore protect against untrusted fabs. We evaluate our scheme for various designs at the physical, DRC-clean layout level. Our scheme incurs a significantly lower cost than most of the prior art. Notably, for fully camouflaged layouts, we observe average power, performance, and area overheads of 24.96%, 19.06%, and 32.55%, respectively. We conduct a thorough security study addressing the threats (attacks) related to untrustworthy FEOL fabs (proximity attacks) and malicious end-users (SAT-based attacks). An empirical key finding is that only large-scale camouflaging schemes like ours are practically secure against powerful SAT-based attacks. Another key finding is that our scheme hinders both placement- and routing-centric proximity attacks; correct connections are reduced by $7.47\times $ , and complexity is increased by $24.15\times $ , respectively, for such attacks.

Obfuscating the interconnects: low-cost and resilient full-chip layout camouflaging

/pdf/large-scale-3d-chips-challenges-and-solutions-for-design-3khhbe321s.pdf

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Despite numerous advantages of 3-D integrated circuits (ICs), their commercial success remains limited. In part, this is due to the wide availability of trustworthy intellectual property (IP) blocks developed for 2-D ICs and proven through repeated use. Block-based design reuse is imperative for heterogeneous 3-D ICs where memory, logic, analog, and microelectromechanical systems dies are manufactured at different technology nodes and circuit modules cannot be partitioned among several dies. In this paper, we show how to integrate 2-D IP blocks into 3-D chips without altering their layout. Experiments indicate that the overhead of proposed integration is small, which can help accelerate industry adoption of 3-D integration.

/pdf/assembling-2-d-blocks-into-3-d-chips-1bgpm65d4c.pdf

Assembling 2-D Blocks Into 3-D Chips

Protecting intellectual property (IP) in electronic circuits has become a serious challenge in recent years. Logic locking/encryption and layout camouflaging are two prominent techniques for IP protection. Most existing approaches, however, particularly those focused on CMOS integration, incur excessive design overheads resulting from their need for additional circuit structures or device-level modifications. This work leverages the innate polymorphism of an emerging spin-based device, called the giant spin-Hall effect (GSHE) switch, to simultaneously enable locking and camouflaging within a single instance. Using the GSHE switch, we propose a powerful primitive that enables cloaking all the 16 Boolean functions possible for two inputs. We conduct a comprehensive study using state-of-the-art Boolean satisfiability (SAT) attacks to demonstrate the superior resilience of the proposed primitive in comparison to several others in the literature. While we tailor the primitive for deterministic computation, it can readily support stochastic computation; we argue that stochastic behavior can break most, if not all, existing SAT attacks. Finally, we discuss the resilience of the primitive against various side-channel attacks as well as invasive monitoring at runtime, which are arguably even more concerning threats than SAT attacks.

Advancing hardware security using polymorphic and stochastic spin-hall effect devices

Split manufacturing is a promising technique to defend against fab-based malicious activities such as IP piracy, overbuilding, and insertion of hardware Trojans. However, a network flow-based proximity attack, proposed by Wang et al. (DAC'16) [1], has demonstrated that most prior art on split manufacturing is highly vulnerable. Here in this work, we present two practical layout techniques towards secure split manufacturing: (i) gate-level graph coloring and (ii) clustering of same-type gates. Our approach shows promising results against the advanced proximity attack, lowering its success rate by 5.27x, 3.19x, and 1.73x on average compared to the unprotected layouts when splitting at metal layers M1, M2, and M3, respectively. Also, it largely outperforms previous defense efforts; we observe on average 8x higher resilience when compared to representative prior art. At the same time, extensive simulations on ISCAS'85 and MCNC benchmarks reveal that our techniques incur an acceptable layout overhead. Apart from this empirical study, we provide — for the first time — a theoretical framework for quantifying the layout-level resilience against any proximity-induced information leakage. Towards this end, we leverage the notion of mutual information and provide extensive results to validate our model.

Johann Knechtel

Papers

Obfuscating the interconnects: low-cost and resilient full-chip layout camouflaging

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Assembling 2-D Blocks Into 3-D Chips

Advancing hardware security using polymorphic and stochastic spin-hall effect devices

Rethinking split manufacturing: an information-theoretic approach with secure layout techniques