Johannes Maximilian Kühn

Bio: Johannes Maximilian Kühn is an academic researcher from University of Tübingen. The author has contributed to research in topics: Dependability & Abstraction (linguistics). The author has an hindex of 6, co-authored 17 publications receiving 102 citations. Previous affiliations of Johannes Maximilian Kühn include Keio University.

Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization

Abstract: Body bias control is a fundamental technique widely used to provide an efficient tradeoff between leakage power and performance in ultralow-power systems. Therefore, a lot of research about power optimization which provides optimal power supply and body bias voltages has been carried out. However, considering the actual voltage sources, the conventional approaches suffer from limited performance/power control granularity and may lead to degradation in terms of the energy efficiency. Therefore, in this paper, a power optimization method that improves the performance/power control granularity is proposed and evaluated with real processor chips. In the proposed optimization, the body biases for nMOSFET and pMOSFET are controlled independently, while the conventional methods control them uniformly. This increases the number of possible voltage combinations and allows finer target frequency selection leading to lower power consumption than the conventional methods at the cost of the optimization complexity. In order to ease this complexity, the proposed optimization is based on simple power and delay models. The model-based optimization does not require brute force search in the phase of real chip testing; thus, the testing time and cost can be significantly reduced. Since the coefficients of the models are extracted with real chip measurements, the error of the model can be suppressed to a few percent in average. The proposed approach is validated by real chips implemented with a 65-nm fully depleted silicon on insulator technology. The evaluation results show that the proposed optimization is an efficient mean of power reduction for a leakage current dominant chip. In fact, when compared with the conventional method, the proposed approach achieves 9.617% of average power reduction reaching up to 22.77% in the case of the V850 microcontroller.

Leveraging FDSOI through body bias domain partitioning and bias search

Abstract: In FDSOI, sophisticated body biasing schemes can greatly reduce leakage or improve performance as well as efficiency. This paper proposes algorithms to determine body bias domain candidates which then merge those to reach a desired number of domains. Domain candidates are determined using an activation based approach, analyzing mapped verilog netlists to identify which parts of the design are used under specified conditions. Body bias domain partitionings are then determined based on activation and the timing of the partitioned parts. The algorithms include a body bias assignment algorithm to reach given timing goals with multiple domains and cross-domain resource sharing. The approach is compatible with any synthesis optimization and is resource sharing aware. Using an implementation of the proposed algorithms, overall leakage can be significantly reduced in all scenarios while obtaining the same benefits of body biasing. The method is evaluated in STMicro's 28nm FDSOI and Renesas's 65nm SOTB.

A Fast and Accurate FPGA-Based Fault Injection System

Abstract: This paper introduces an FPGA-based fault injection system. To realize this system a library was developed, which implements a static mapping between a circuit described at RTL or gate-level and its corresponding placed and routed FPGA design. The aim of this mapping is to preserve module and port structure of the placed and routed FPGA design to the RT/gate-level circuit description. To demonstrate the accuracy of this mapping the ISCAS'89 benchmark circuits and the VHDL netlist of the LEON3 system are used. The results show that about 99% of the ports in the RT/gate-level circuit description can be located in the placed and routed FPGA design. Based on this library a fault injection tool was developed to accelerate the fault injection experiment time by bypassing some stages (synthesis, placement and routing) of a re-compilation process. In these experiments a 12 × speedup was achieved when compared to fault injections based on serial fault emulation.

A Survey on Industrial Information Integration 2016–2019

Abstract: Industrial information integration engineering (IIIE) is a set of foundational concepts and techniques that facilitate the industrial information integration process. In recent years, many applicat...

Multi-Layer Dependability: From Microarchitecture to Application Level

Abstract: We show in this paper that multi-layer dependability is an indispensable way to cope with the increasing amount of technology-induced dependability problems that threaten to proceed further scaling. We introduce the definition of multi-layer dependability and present our design flow within this paradigm that seamlessly integrates techniques starting at circuit layer all the way up to application layer and thereby accounting for ASIC-based architectures as well as for reconfigurable-based architectures. At the end, we give evidence that the paradigm of multi-layer dependability bears a large potential for significantly increasing dependability at reasonable effort.

Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges

Abstract: Intelligent automotive electronics significantly improved driving safety in the last decades. With the increasing complexity of automotive systems, dependability of the electronic components themselves and of their interaction must be assured to avoid any risk to driving safety due to unexpected failures caused by internal or external faults.Additionally, Virtual Prototypes (VPs) have been accepted in many areas of system development processes in the automotive industry as platforms for SW development, verification, and design space exploration. We believe that VPs will significantly contribute to the analysis of safety conditions for automotive electronics. This paper shows the advantages of such a methodology based on today's industrial needs, presents the current state of the art in this field, and outlines upcoming research challenges that need to be addressed to make this vision a reality.

From Layout to System: Early Stage Power Delivery and Architecture Co-Exploration

Abstract: With the reduced noise margin brought by relentless technology scaling, power integrity assurance has become more challenging than ever. On the other hand, traditional design methodologies typically focus on a single design layer without much cross-layer interaction, potentially introducing unnecessary guard-band and wasting significant design resources. Both issues imperatively call for a cross-layer framework for the co-exploration of power delivery (PD) and system architecture, especially in the early design stage with larger design and optimization freedom. Unfortunately, such a framework does not exist yet in the literature. As a step forward, this paper provides a run-time simulation framework of both PD and architecture and captures their interactions. Enabled by the proposed recursive run-time PD model, it can achieve smaller than 1% deviation from SPICE for an entire PD system simulation. Moreover, with seamless interactions among architecture, power and PD simulators, it can simulate actual benchmarks within reasonable time. The experimental results of running PARSEC suite have demonstrated the framework’s capability to discover the co-effect of PD and architecture for early stage design optimization. Moreover, it also shows multiple over-pessimism in traditional PD methodologies. Finally, the framework is able to investigate the impact of dynamic noise on system level oxide breakdown reliability and shows 31%–92% lifetime estimation deviations from typical static analysis.

Reliability challenges for electric vehicles: from devices to architecture and systems software

Abstract: Today, modern high-end cars have close to 100 electronic control units (ECUs) that are used to implement a variety of applications ranging from safety-critical control to driver assistance and comfort-related functionalities. The total sum of these applications is several million lines of software code. The ECUs are connected to different sensors and actuators and communicate via a variety of communication buses like CAN, FlexRay and now also Ethernet. In the case of electric vehicles, both the amount and the importance of such electronics and software are even higher. Here, a number of hydraulic or pneumatic controls are replaced by corresponding software-implemented controllers in order to reduce the overall weight of the car and hence to improve its driving range. Until recently, most of the software and system design in the automotive domain -- as in many other domains -- relied on an always correctly functioning or a zero-defect hardware implementation platform. However, as the device geometries of integrated circuits continue to shrink, this assumption is increasingly not true. Incorporating large safety margins in the design process results in very pessimistic design and expensive processors. Further, the processors in cars -- in contrast to those in many consumer electronics devices like mobile phones -- are exposed to harsh environments, extreme temperature variations, and often, strong electromagnetic fields. Hence, their reliability is even more questionable and must be explicitly accounted for in all layers of design abstraction -- starting from circuit design to architecture design, to software design and runtime management and monitoring. In this paper we outline some of these issues, currently followed practices, and the challenges that lie ahead of us in the automotive and electric vehicles domain.