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Author

John H. Magerlein

Other affiliations: Veeco, GlobalFoundries
Bio: John H. Magerlein is an academic researcher from IBM. The author has contributed to research in topics: Microchannel & Thermal resistance. The author has an hindex of 22, co-authored 51 publications receiving 1935 citations. Previous affiliations of John H. Magerlein include Veeco & GlobalFoundries.


Papers
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Journal ArticleDOI
01 Feb 2013
TL;DR: This study considers multiphysics applications from algorithmic and architectural perspectives, where “algorithmic” includes both mathematical analysis and computational complexity, and “architectural’ includes both software and hardware environments.
Abstract: We consider multiphysics applications from algorithmic and architectural perspectives, where “algorithmic” includes both mathematical analysis and computational complexity, and “architectural” includes both software and hardware environments. Many diverse multiphysics applications can be reduced, en route to their computational simulation, to a common algebraic coupling paradigm. Mathematical analysis of multiphysics coupling in this form is not always practical for realistic applications, but model problems representative of applications discussed herein can provide insight. A variety of software frameworks for multiphysics applications have been constructed and refined within disciplinary communities and executed on leading-edge computer systems. We examine several of these, expose some commonalities among them, and attempt to extrapolate best practices to future systems. From our study, we summarize challenges and forecast opportunities.

278 citations

Journal ArticleDOI
TL;DR: In this paper, the authors describe a practical implementation of a single-phase Si microchannel cooler designed for cooling very high power chips such as microprocessors, which is able to cool chips with average power densities of 400W/cm2 or more.
Abstract: This paper describes a practical implementation of a single-phase Si microchannel cooler designed for cooling very high power chips such as microprocessors. Through the use of multiple heat exchanger zones and optimized cooler fin designs, a unit thermal resistance 10.5 C-mm2 /W from the cooler surface to the inlet water was demonstrated with a fluid pressure drop of <35kPa. Further, cooling of a thermal test chip with a microchannel cooler bonded to it packaged in a single chip module was also demonstrated for a chip power density greater than 300W/cm2. Coolers of this design should be able to cool chips with average power densities of 400W/cm2 or more

208 citations

Proceedings ArticleDOI
04 Jun 2007
TL;DR: 3D chip technologies come in a number of flavors, but are expected to enable the extension of CMOS performance, which forces the industry to look at formerly-two- dimensional integration issues quite differently, and requires the re-fitting of multiple existing EDA capabilities.
Abstract: Despite generation upon generation of scaling, computer chips have until now remained essentially 2-dimensional. Improvements in on-chip wire delay and in the maximum number of I/O per chip have not been able to keep up with transistor performance growth; it has become steadily harder to hide the discrepancy. 3D chip technologies come in a number of flavors, but are expected to enable the extension of CMOS performance. Designing in three dimensions, however, forces the industry to look at formerly-two- dimensional integration issues quite differently, and requires the re-fitting of multiple existing EDA capabilities.

202 citations

Proceedings ArticleDOI
15 Mar 2005
TL;DR: In this article, the authors describe a practical implementation of a single-phase Si microchannel cooler designed for cooling very high power chips such as microprocessors, achieving a unit thermal resistance of 10.5 C-mm/sup 2/W from the cooler surface to the inlet water with a fluid pressure drop of less than 35 kPa.
Abstract: The paper describes a practical implementation of a single-phase Si microchannel cooler designed for cooling very high power chips such as microprocessors. Through the use of multiple heat exchanger zones and optimized cooler fin designs, a unit thermal resistance of 10.5 C-mm/sup 2//W from the cooler surface to the inlet water was demonstrated with a fluid pressure drop of less than 35 kPa. Further, cooling of a thermal test chip with a microchannel cooler bonded to it packaged in a single chip module was also demonstrated for a chip power density greater than 300 W/cm/sup 2/. Coolers of this design should be able to cool chips with average power densities of 400 W/cm/sup 2/ or more.

202 citations

Patent
01 Jul 2004
TL;DR: In this article, an integrated microchannel cooler device (or microchannel heat sink device) for cooling IC chips is designed to provide uniform flow and distribution of coolant fluid and minimize pressure drops along coolant flow paths, as well as variable localized cooling capabilities for high power density regions (or hot spots) of IC chips with higher than average power densities.
Abstract: Apparatus and methods are provided for microchannel cooling of electronic devices such as IC chips, which enable efficient and low operating pressure microchannel cooling of high power density electronic devices having a non-uniform power density distribution, which are mounted face down on a package substrate. For example, integrated microchannel cooler devices (or microchannel heat sink devices) for cooling IC chips are designed to provide uniform flow and distribution of coolant fluid and minimize pressure drops along coolant flow paths, as well as provide variable localized cooling capabilities for high power density regions (or “hot spots”) of IC chips with higher than average power densities.

128 citations


Cited by
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Patent
01 Aug 2008
TL;DR: In this article, the oxide semiconductor film has at least a crystallized region in a channel region, which is defined as a region of interest (ROI) for a semiconductor device.
Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

1,501 citations

01 Jan 1999
TL;DR: Damascene copper electroplating for on-chip interconnections, a process that was conceived and developed in the early 1990s, makes it possible to fill submicron trenches and vias with copper without creating a void or a seam and has thus proven superior to other technologies of copper deposition as discussed by the authors.
Abstract: Damascene copper electroplating for on-chip interconnections, a process that we conceived and developed in the early 1990s, makes it possible to fill submicron trenches and vias with copper without creating a void or a seam and has thus proven superior to other technologies of copper deposition. We discuss here the relationship of additives in the plating bath to superfilling, the phenomenon that results in superconformal coverage, and we present a numerical model which accounts for the experimentally observed profile evolution of the plated metal.

1,006 citations

Book ChapterDOI
01 Jan 1985
TL;DR: The first group of results in fixed point theory were derived from Banach's fixed point theorem as discussed by the authors, which is a nice result since it contains only one simple condition on the map F, since it is easy to prove and since it nevertheless allows a variety of applications.
Abstract: Formally we have arrived at the middle of the book. So you may need a pause for recovering, a pause which we want to fill up by some fixed point theorems supplementing those which you already met or which you will meet in later chapters. The first group of results centres around Banach’s fixed point theorem. The latter is certainly a nice result since it contains only one simple condition on the map F, since it is so easy to prove and since it nevertheless allows a variety of applications. Therefore it is not astonishing that many mathematicians have been attracted by the question to which extent the conditions on F and the space Ω can be changed so that one still gets the existence of a unique or of at least one fixed point. The number of results produced this way is still finite, but of a statistical magnitude, suggesting at a first glance that only a random sample can be covered by a chapter or even a book of the present size. Fortunately (or unfortunately?) most of the modifications have not found applications up to now, so that there is no reason to write a cookery book about conditions but to write at least a short outline of some ideas indicating that this field can be as interesting as other chapters. A systematic account of more recent ideas and examples in fixed point theory should however be written by one of the true experts. Strange as it is, such a book does not seem to exist though so many people are puzzling out so many results.

994 citations

Journal ArticleDOI
TL;DR: Results confirm the unique benefits for future generations of CMPs that can be achieved by bringing optics into the chip in the form of photonic NoCs, as well as a comparative power analysis of a photonic versus an electronic NoC.
Abstract: The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die We present photonic networks-on-chip (NoC) as a solution to reduce the impact of intra-chip and off-chip communication on the overall power budget A photonic interconnection network can deliver higher bandwidth and lower latencies with significantly lower power dissipation We explain why on-chip photonic communication has recently become a feasible opportunity and explore the challenges that need to be addressed to realize its implementation We introduce a novel hybrid micro-architecture for NoCs combining a broadband photonic circuit-switched network with an electronic overlay packet-switched control network We address the critical design issues including: topology, routing algorithms, deadlock avoidance, and path-setup/tear-down procedures We present experimental results obtained with POINTS, an event-driven simulator specifically developed to analyze the proposed idea, as well as a comparative power analysis of a photonic versus an electronic NoC Overall, these results confirm the unique benefits for future generations of CMPs that can be achieved by bringing optics into the chip in the form of photonic NoCs

873 citations

Journal ArticleDOI
TL;DR: In this article, the authors show that the enhancement in the effective thermal conductivity of nanofluids is due mainly to localized convection caused by the Brownian movement of the nanoparticles.
Abstract: Here we show through an order-of-magnitude analysis that the enhancement in the effective thermal conductivity of nanofluids is due mainly to the localized convection caused by the Brownian movement of the nanoparticles. We also introduce a convective-conductive model which accurately captures the effects of particle size, choice of base liquid, thermal interfacial resistance between the particles and liquid, temperature, etc. This model is a combination of the Maxwell-Garnett (MG) conduction model and the convection caused by the Brownian movement of the nanoparficles, and reduces to the MG model for large particle sizes. The model is in good agreement with data on water, ethylene glycol, and oil-based nanofluids, and shows that the lighter the nanoparticles, the greater the convection effect in the liquid, regardless of the thermal conductivity of the nanoparticles.

512 citations