J
John M. Cohn
Researcher at IBM
Publications - 86
Citations - 2738
John M. Cohn is an academic researcher from IBM. The author has contributed to research in topics: Integrated circuit & Design layout record. The author has an hindex of 26, co-authored 84 publications receiving 2502 citations. Previous affiliations of John M. Cohn include Carnegie Mellon University.
Papers
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Proceedings ArticleDOI
Managing power and performance for system-on-chip designs using Voltage Islands
David E. Lackey,Paul S. Zuchowski,Thomas R. Bednar,Douglas W. Stout,Scott Whitney Gould,John M. Cohn +5 more
TL;DR: In this article, the authors discuss Voltage Islands, a system architecture and chip implementation methodology that can be used to dramatically reduce active and static power consumption for System-on-Chip (SoC) designs.
Journal ArticleDOI
KOAN/ANAGRAM II: new tools for device-level analog placement and routing
TL;DR: KOAN and ANAGRAM II differ from previous approaches by using general algorithmic techniques to find critical device-level layout optimizations rather than relying on a large library of fixed-topology module generators.
KOAN/ANAGRAM 11: New Tools for Device-Level Analog Placement and Routing
TL;DR: In this article, the authors describe a new tool for device-level analog placement and routing called KOAN and ANAGRAM II, which uses general algorithmic techniques to find critical devicelevel layout optimizations rather than relying on a large library of fixed-topology module generators.
Proceedings Article
MCUNet: Tiny Deep Learning on IoT Devices
TL;DR: MCUNet, a framework that jointly designs the efficient neural architecture (T TinyNAS) and the lightweight inference engine (TinyEngine), enabling ImageNet-scale inference on microcontrollers, is proposed, suggesting that the era of always-on tiny machine learning on IoT devices has arrived.
Proceedings ArticleDOI
Pushing ASIC performance in a power envelope
Ruchir Puri,Leon Stok,John M. Cohn,David S. Kung,David Z. Pan,Dennis Sylvester,Ashish Srivastava,Sarvesh H. Kulkarni +7 more
TL;DR: The trade-off between multiple supply voltages and multiple threshold voltages in the optimization of dynamic and static power is explored and optimization techniques such as clock skew scheduling are discussed which can be effectively used to push performance in a power neutral way.