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John Wallberg

Bio: John Wallberg is an academic researcher from Texas Instruments. The author has contributed to research in topics: Phase-locked loop & CMOS. The author has an hindex of 22, co-authored 36 publications receiving 2999 citations.

Papers
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Journal ArticleDOI
TL;DR: The first all-digital PLL and polar transmitter for mobile phones is presented, exploiting the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom.
Abstract: We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5/spl deg/ rms phase error, -165 dBc/Hz phase noise at 20 MHz offset, and 10 /spl mu/s settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm/sup 2/ and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power.

695 citations

Journal ArticleDOI
TL;DR: In this paper, the authors present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process, which is compatible with digital deep-submicron CMOS processes and can be readily integrated with a digital baseband and application processor.
Abstract: We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm/sup 2/ and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

566 citations

Journal ArticleDOI
TL;DR: A 20-ps time-to-digital converter (TDC) realized in 90-nm digital CMOS is used as a phase/frequency detector and charge pump replacement in an all-digital phase-locked loop for a fully-compliant Global System for Mobile Communications (GSM) transceiver.
Abstract: We propose and demonstrate a 20-ps time-to-digital converter (TDC) realized in 90-nm digital CMOS. It is used as a phase/frequency detector and charge pump replacement in an all-digital phase-locked loop for a fully-compliant Global System for Mobile Communications (GSM) transceiver. The TDC core is based on a pseudodifferential digital architecture that makes it insensitive to nMOS and pMOS transistor mismatches. The time conversion resolution is equal to an inverter propagation delay, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with the estimation accuracy better than 1%. It additionally serves as a CMOS process strength estimator for analog circuits in this large system-on-chip. Measured integral nonlinearity is 0.7 least significant bits. The TDC consumes 5.3 mA raw and 1.3 mA with power management from a 1.3-V supply.

366 citations

Proceedings ArticleDOI
29 Aug 2005
TL;DR: A 1.2V 42mA all-digital PLL and polar transmitter for a single-chip GSM/EDGE transceiver is implemented in 90nm CMOS and achieves -165dBc/Hz phase noise at 20MHz offset, with 10 /spl mu/s settling time.
Abstract: A 1.2V 42mA all-digital PLL and polar transmitter for a single-chip GSM/EDGE transceiver is implemented in 90nm CMOS. It transmits GMSK with 0.5/spl deg/ rms phase error and achieves -165dBc/Hz phase noise at 20MHz offset, with 10 /spl mu/s settling time. A digitally controlled 6dBm class-E PA modulates the amplitude and meets the EDGE spectral mask with 3.5% EVM.

176 citations

Proceedings ArticleDOI
13 Sep 2004
TL;DR: A discrete-time receiver architecture for a wireless application is presented and analog signal processing concepts are used to directly sample the RF input at Nyquist rate.
Abstract: A discrete-time receiver architecture for a wireless application is presented. Analog signal processing concepts are used to directly sample the RF input at Nyquist rate. Maximum receiver sensitivity is -83dBm and the chip consumes a total of 41mA from a 1.575V internally regulated supply. The receiver is implemented in a 0.13/spl mu/m digital CMOS process.

136 citations


Cited by
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Journal ArticleDOI
TL;DR: The first all-digital PLL and polar transmitter for mobile phones is presented, exploiting the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom.
Abstract: We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5/spl deg/ rms phase error, -165 dBc/Hz phase noise at 20 MHz offset, and 10 /spl mu/s settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm/sup 2/ and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power.

695 citations

Journal ArticleDOI
TL;DR: In this paper, the authors present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process, which is compatible with digital deep-submicron CMOS processes and can be readily integrated with a digital baseband and application processor.
Abstract: We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm/sup 2/ and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

566 citations

Journal ArticleDOI
TL;DR: A new coarse-fine TDC architecture is proposed by using an array of time amplifiers and two identical fine TDCs that compensate for the variation of the TA gain during the conversion process, which will improve the linearity further.
Abstract: This paper presents the design of a coarse-fine time-to-digital converter (TDC) that amplifies a time residue to improve time resolution, similar to a coarse-fine analog-to-digital converter (ADC). A new digital circuit has been developed to amplify the time residue with a higher gain (>16) and larger range (>80 ps) than existing solutions do. However, adapting the conventional coarse-fine architecture from ADCs is not an appropriate solution for TDCs: input time cannot be stored, and the gain of a time amplifier (TA) cannot be controlled precisely. This paper proposes a new coarse-fine TDC architecture by using an array of time amplifiers and two identical fine TDCs that compensate for the variation of the TA gain during the conversion process. The measured DNL and INL are plusmn0.8 LSB and plusmn3 LSB, respectively, with a value of 1.25 ps per 1 LSB, while the standard deviation of output code for constant inputs remains below 1 LSB across the TDC range. Although the nonlinearity is larger than 1 LSB, using an INL lookup table or better matched delays in the coarse TDC delay chain will improve the linearity further.

465 citations

Journal ArticleDOI
TL;DR: The receiver's flexible analog baseband samples the channel of interest at zero IF, and is followed by clock-programmable downsampling with embedded filtering, giving a tunable selectivity that exceeds that of an RF prefilter, and a conversion rate that is low enough for A/D conversion at only milliwatts.
Abstract: After being the subject of speculation for many years, a software-defined radio receiver concept has emerged that is suitable for mobile handsets. A key step forward is the realization that in mobile handsets, it is enough to receive one channel with any bandwidth, situated in any band. Thus, the front-end can be tuned electronically. Taking a cue from a digital front-end, the receiver's flexible analog baseband samples the channel of interest at zero IF, and is followed by clock-programmable downsampling with embedded filtering. This gives a tunable selectivity that exceeds that of an RF prefilter, and a conversion rate that is low enough for A/D conversion at only milliwatts. The front-end consists of a wideband low noise amplifier and a mixer tunable by a wideband LO. A 90-nm CMOS prototype tunes 200 kHz to 20-MHz-wide channels located anywhere from 800 MHz to 6 GHz

438 citations

Journal ArticleDOI
TL;DR: In this paper, a software-defined radio receiver is designed from a low-power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters.
Abstract: A software-defined radio receiver is designed from a low-power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters. To cover the major frequency bands in use today, a wideband RF front-end, including the low-noise amplifier (LNA) and a wide tuning-range synthesizer, spanning over 800 MHz to 6 GHz is designed. The wideband LNA provides 18-20 dB of maximum gain and 3-3.5 dB of noise figure over 800 MHz to 6 GHz. A low 1/f noise and high-linearity mixer is designed which utilizes the passive mixer core properties and provides around +70 dBm IIP2 over the bandwidth of operation. The entire receiver circuits are implemented in 90-nm CMOS technology. Programmability of the receiver is tested for GSM and 802.11g standards

433 citations