Jonathan A. Noquil

Bio: Jonathan A. Noquil is an academic researcher from Texas Instruments. The author has contributed to research in topics: Quad Flat No-leads package & Die (integrated circuit). The author has an hindex of 16, co-authored 50 publications receiving 656 citations. Previous affiliations of Jonathan A. Noquil include Fairchild Semiconductor International, Inc..

Semiconductor die package including carrier with mask and semiconductor die

Abstract: A carrier for use in a semiconductor die package is disclosed. In one embodiment, the carrier includes a die attach region and an edge region. A solder mask is on the edge region.

Multi-flip chip on lead frame on over molded IC package and method of assembly

Abstract: A multichip module package uses bond wire with plastic resin on one side of a lead frame to package an integrated circuit and flip chip techniques to attach one or more mosfets to the other side of the lead frame. The assembled multichip module 30 has an integrated circuit controller 14 on a central die pad. Wire bonds 16 extend from contact areas on the integrated circuit to outer leads 2.6 of the lead frame 10. On the opposite, lower side of the central die pad, the sources and gates of the mosfets 24, 26 are bump or stud attached to the half etched regions of the lead frame. The drains 36 of the mosfets and the ball contacts 22.1 on the outer leads are soldered to a printed circuit board.

Method to manufacture a universal footprint for a package with exposed chip

Abstract: A semiconductor die package is disclosed. It may include a semiconductor die having a first surface and a second surface, and a leadframe structure. A molding material may be formed around at least a portion of the die and at least a portion of the leadframe structure. A solderable layer may be on the exterior surface of the molding material and the first surface of the semiconductor die.

Semiconductor device package and method of assembly thereof

Abstract: A semiconductor die package includes: an assembly including a semiconductor die, a clip structure attached to an upper surface of the semiconductor die, and a heat sink attached to an upper surface of the clip structure; and a molding material partially encapsulating the assembly, wherein an upper surface of the heat sink is exposed through the molding material.

Integrating multi-output power converters having vertically stacked semiconductor chips

Abstract: A packaged multi-output converter (200) comprising a leadframe with a chip pad (201) as ground terminal and a plurality of leads (202) including the electrical input terminal (203); a first FET chip (sync chip, 220) with its source terminal affixed to the leadframe and on its opposite surface a first drain terminal (221) positioned adjacent to a second drain terminal (222), the drain terminals connected respectively by a first (241) and a second (242) metal clip to a first (204) and second (205) output lead; a second FET chip (control chip, 211), positioned vertically over the first drain terminal, with its source terminal attached onto the first clip; a third FET chip (control chip, 212), positioned vertically over the second drain terminal, with its source terminal attached onto the second clip; and the drain terminals (213, 214) of the second and third chips attached onto a third metal clip (260) connected to the input lead (203).

Display panel and display device

Abstract: A display panel and a display device are provided. The display panel comprises a central region and peripheral regions. The peripheral regions are provided at two opposite ends of the display panel and have a first curvature; the central region is provided between the two opposite ends of the display panel and has a second curvature; and the second curvature of the central region is smaller than the first curvature of the peripheral regions.

Semiconductor die package and method for making the same

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Semiconductor die package using leadframe and clip and method of manufacturing

Abstract: A clip structure for a semiconductor package is disclosed. The clip structure includes a major portion, at least one pedestal extending from the major portion, a downset portion, and a lead portion. The downset portion is between the lead portion and the major portion. The clip structure can be used in a MLP (micro-leadframe package).

Robust leaded molded packages and methods for forming the same

Abstract: A method for making a flip chip in a leaded molded package is disclosed. In some embodiments, the method includes using a leadframe structure including a die attach region and leads. The die attach region includes depressions proximate the inner portions of the leads, and an aperture in the die attach region. A semiconductor die is mounted to the die attach region. A molding material passes through the aperture and covers the first surface of the semiconductor die and the die attach region.

Carrier with metal bumps for semiconductor die packages

Abstract: A carrier for a semiconductor die package is disclosed. In one embodiment, the carrier includes a metal layer and a plurality of bumps formed in the metal layer. The bumps can be formed by stamping.